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Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect

https://doi.org/10.1145/2890499
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4419-6911-8_10openalex-snapshot
RF-Interconnect for Future Network-On-Chip
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/5.920578openalex-snapshot
RF/wireless interconnect for inter- and intra-chip communications
inferredcites →https://doi.org/10.1109/aspdac.2010.5419825openalex-snapshot
Floorplanning and topology generation for application-specific Network-on-Chip
inferredcites →https://doi.org/10.1109/hpca.2008.4658639openalex-snapshot
CMP network-on-chip overlaid with multi-band RF-interconnect
inferredcites →https://doi.org/10.1109/iccd.2003.1240887openalex-snapshot
Efficient synthesis of networks on chip
inferredcites →https://doi.org/10.1109/isqed.2007.139openalex-snapshot
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals
inferredcites →https://doi.org/10.1109/isscc.1994openalex-snapshot
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94
inferredcites →https://doi.org/10.1109/les.2015.2402197openalex-snapshot
ORION3.0: A Comprehensive NoC Router Estimation Tool
inferredcites →https://doi.org/10.1109/mm.2007.4378787openalex-snapshot
Research Challenges for On-Chip Interconnection Networks
inferredcites →https://doi.org/10.1109/sbcci.2003.1232795openalex-snapshot
Proceedings 16th Symposium on Integrated Circuits and Systems Design. SBCCI 2003
inferredcites →https://doi.org/10.1109/sbcci.2012.6344421openalex-snapshot
Application-Specific Network-on-Chip synthesis with topology-aware floorplanning
inferredcites →https://doi.org/10.1109/tcad.2008.2010691openalex-snapshot
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
inferredcites →https://doi.org/10.1109/tcad.2008.917968openalex-snapshot
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs
inferredcites →https://doi.org/10.1109/tcad.2010.2061610openalex-snapshot
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips
inferredcites →https://doi.org/10.1109/tcad.2014.2331556openalex-snapshot
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies
inferredcites →https://doi.org/10.1109/tnet.2003.813040openalex-snapshot
Application of network calculus to general topologies using turn-prohibition
inferredcites →https://doi.org/10.1109/tpds.2005.22openalex-snapshot
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
inferredcites →https://doi.org/10.1109/tvlsi.2006.871762openalex-snapshot
Linear-programming-based techniques for synthesis of network-on-chip architectures
inferredcites →https://doi.org/10.1109/tvlsi.2012.2195688openalex-snapshot
CusNoC: Fast Full-Chip Custom NoC Generation
inferredcites →https://doi.org/10.1145/1233501.1233573openalex-snapshot
Designing application-specific networks on chips with floorplan information
inferredcites →https://doi.org/10.1145/1353629.1353649openalex-snapshot
RF interconnects for communications on-chip
inferredcites →https://doi.org/10.1145/2000064.2000078openalex-snapshot
TLSync
inferredcites →https://doi.org/10.1145/2024723.2000078openalex-snapshot
TLSync
inferredcites →https://doi.org/10.1145/2159542.2159544openalex-snapshot
Optimized 3D Network-on-Chip Design Using Simulated Allocation
inferredcites →https://doi.org/10.1145/2333660.2333669openalex-snapshot
Practically scalable floorplanning with voltage island generation
inferredcites →https://doi.org/10.1145/332357.332401openalex-snapshot
Classical floorplanning harmful?
inferredcites →https://doi.org/10.1145/378239.379048openalex-snapshot
Route packets, net wires
inferredcites →https://doi.org/10.1587/transele.e95.c.534openalex-snapshot
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips
inferredcites →https://doi.org/10.1587/transfun.e96.a.1174openalex-snapshot
Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips
inferredcites →https://doi.org/10.5555/1356802.1356871openalex-snapshot
Application-specific network-on-chip architecture synthesis based on set partitions and Steiner trees
inferredcites →https://doi.org/10.5555/2132325.2132471openalex-snapshot
A tree-based topology synthesis for on-chip network

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.nancom.2018.12.001openalex-snapshot
Energy-aware and fault-tolerant custom topology design method for network-on-chips
inferred← citeshttps://doi.org/10.1016/j.nancom.2019.01.005openalex-snapshot
H2WNoC: A honeycomb hardware-efficient wireless network-on-chip architecture
inferred← citeshttps://doi.org/10.1016/j.vlsi.2018.02.012openalex-snapshot
Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems
inferred← citeshttps://doi.org/10.1049/iet-cdt.2018.5202openalex-snapshot
Mapping application‐specific topology to mesh topology with reconfigurable switches
inferred← citeshttps://doi.org/10.1109/asicon.2017.8252420openalex-snapshot
Integer linear programming based fault-tolerant topology synthesis for application-specific NoC
inferred← citeshttps://doi.org/10.1109/etncc59188.2023.10284966openalex-snapshot
An Artificial Bee Colony Based Mapping Method for Three Dimensional Network-on-Chip
inferred← citeshttps://doi.org/10.1109/slip.2017.7974907openalex-snapshot
Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs
inferred← citeshttps://doi.org/10.1109/tcad.2017.2650989openalex-snapshot
TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip
inferred← citeshttps://doi.org/10.1109/tcad.2019.2952134openalex-snapshot
Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips
inferred← citeshttps://doi.org/10.1145/3450504openalex-snapshot
Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems
inferred← citeshttps://doi.org/10.1145/3480961openalex-snapshot
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips
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