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Efficient synthesis of networks on chip
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4613-0457-9openalex-snapshot
Mathematical Classification and Clustering
inferredcites →https://doi.org/10.1038/sj.jors.2600836openalex-snapshot
Mathematical Classification and Clustering
inferredcites →https://doi.org/10.1109/2.976918openalex-snapshot
2001 technology roadmap for semiconductors
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/dac.2002.1012729openalex-snapshot
Constraint-driven communication synthesis
inferredcites →https://doi.org/10.1109/iccad.2000.896509openalex-snapshot
Efficient exploration of the SoC communication architecture design space
inferredcites →https://doi.org/10.1145/513918.514114openalex-snapshot
Constraint-driven communication synthesis
inferredcites →https://doi.org/10.5555/602902.602998openalex-snapshot
Efficient exploration of the SoC communication architecture design space
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Designing Routing and Message-Dependent Deadlock Free Networks on Chips
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System-Level Design of Network-on-Chip Architectures
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3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks
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Energy-Efficient Networks-on-Chip Architectures: Design and Run-Time Optimization
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System-Level Application-Specific NoC Design for Network and Multimedia Applications
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Implementation of Application Specific Network-On-Chip Architectures on Reconfigurable Device Using Topology Generation Algorithm with Genetic Algorithm Based Optimization Technique
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Application-Specific NoC Architecture Customization Using Long-Range Links
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Power-Aware Topology Generation Based on Clustering for Application-Specific Network on Chip
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Microarchitecture-Level SoC Design
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Microarchitecture-Level SoC Design
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Privacy-Preserving Parallel Computation of Minimum Spanning Forest
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Arbiter synthesis approach for SoC multi-processor systems
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Communication Centric Floorplanning of NoC Based System on Chip
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Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores
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Quality-of-service and error control techniques for mesh-based network-on-chip architectures
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Network-on-Chip design and synthesis outlook
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Lagrangian relaxation-based routing path allocation for application-specific network-on-chips
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Low-power algorithm for automatic topology generation for application-specific networks on chips
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Communication-Centric SoC Design for Nanoscale Domain
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Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
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SAGA: synthesis technique for guaranteed throughput NoC architectures
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Mapping and configuration methods for multi-use-case networks on chips
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Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms
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Tree-Based Partitioning Approach for Network-on-Chip Synthesis
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×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
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A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
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Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
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An Application-Specific Design Methodology for STbus Crossbar Generation
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A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
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A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures
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Communication architecture optimization: making the shortest path shorter in regular networks-on-chip
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SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
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A method to remove deadlocks in Networks-on-Chips with Wormhole flow control
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Rapid Prototyping of NoC Architectures from a SystemC Specification
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GA Based Congestion Aware Topology Generation for Application Specific NoC
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Network Interface Sharing Techniques for Area Optimized NoC Architectures
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Use of irregular topologies for the synthesis of networks-on-chip
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DNN-based Knee Osteoarthritis Disease Detection using X-Rays
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Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion
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Traffic Driven Automated Synthesis of Network-on-Chip from Physically Aware Behavioral Specification
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From Latency-Insensitive Design to Communication-Based System-Level Design
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Routing Aware Switch Hardware Customization for Networks on Chips
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System level design paradigms
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Computation and communication refinement for multiprocessor SoC design
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Automated technique for design of NoC with minimal communication latency
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NoC topology synthesis for supporting shutdown of voltage islands in SoCs
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Yield enhancement by robust application-specific mapping on Network-on-Chips
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Designing best effort networks-on-chip to meet hard latency constraints
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Fine-Grained Interconnect Synthesis
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Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect
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Application-Specific Network-on-Chip Synthesis
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Opinion Mining and Sentiment Analysis
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Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips
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Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips
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An Inductive-Coupling Interconnected Application-Specific 3D NoC Design
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The Environment for Mapping SystemC Multi-module Specifications onto NoC Architectures
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Customizable Computing
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A system-level design methodology for application-specific networks-on-chip
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Hardware-software co-design and optimization for point-to-point network-on-chip based many-core systems
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Algorithm for the Choice of Topology in Reconfigurable On-Chip Networks with Real-Time Support
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Communication Bandwidth Adaptable Network Design of Complex Application Specific SoC
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An automated technique for topology and route generation of application specific on-chip interconnection networks
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Application-specific network-on-chip architecture customization via long-range link insertion
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Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
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NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
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Application-specific network-on-chip architecture synthesis based on set partitions and Steiner trees
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Synthesis of networks on chips for 3D systems on chips
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A method to remove deadlocks in networks-on-chips with wormhole flow control
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SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
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Low-Power Bus Architecture Composition for AMBA AXI
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