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Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devices

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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1038/nature06932openalex-snapshot

The missing memristor found

inferredcites →https://doi.org/10.1038/nphys1968openalex-snapshot

Vertical-current-induced domain-wall motion in MgO-based magnetic tunnel junctions with low current densities

inferredcites →https://doi.org/10.1063/1.3677340openalex-snapshot

Effects of notch shape on the magnetic domain wall motion in nanowires with in-plane or perpendicular magnetic anisotropy

inferredcites →https://doi.org/10.1109/iedm.2013.6724553openalex-snapshot

20-nm magnetic domain wall motion memory with ultralow-power operation

inferredcites →https://doi.org/10.1109/isscc.2010.5433948openalex-snapshot

A 64Mb MRAM with clamped-reference and adequate-reference schemes

inferredcites →https://doi.org/10.1109/jetcas.2015.2405171openalex-snapshot

Exploring Spin Transfer Torque Devices for Unconventional Computing

inferredcites →https://doi.org/10.1109/jproc.2002.808156openalex-snapshot

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

inferredcites →https://doi.org/10.1109/jproc.2010.2070050openalex-snapshot

Phase Change Memory

inferredcites →https://doi.org/10.1109/led.2013.2279153openalex-snapshot

DSH-MRAM: Differential Spin Hall MRAM for On-Chip Memories

inferredcites →https://doi.org/10.1109/nanoarch.2011.5941494openalex-snapshot

Low-power functionality enhanced computation architecture using spin-based devices

inferredcites →https://doi.org/10.1109/sispad.2011.6035047openalex-snapshot

KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells

inferredcites →https://doi.org/10.1109/tnano.2014.2312177openalex-snapshot

Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

inferredcites →https://doi.org/10.1109/tnano.2015.2437902openalex-snapshot

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks

inferredcites →https://doi.org/10.1109/tnano.2015.2447531openalex-snapshot

An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices

inferredcites →https://doi.org/10.1109/tnnls.2015.2462731openalex-snapshot

Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing

inferredcites →https://doi.org/10.1143/apex.1.091301openalex-snapshot

Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

inferredcites →https://doi.org/10.1145/2228360.2228446openalex-snapshot

mLogic

inferredcites →https://doi.org/10.1145/2333660.2333664openalex-snapshot

Write-optimized reliable design of STT MRAM

inferredcites →https://doi.org/10.1145/2902961.2902994openalex-snapshot

Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate

inferredcites →https://doi.org/10.5555/2755753.2757047openalex-snapshot

Giant spin hall effect (GSHE) logic design for low power application

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.5281/zenodo.6942162openalex-extracted

inferred← citeshttps://doi.org/10.1109/isvlsi.2017.116openalex-snapshot

In-Memory Computing with Spintronic Devices

inferred← citeshttps://doi.org/10.1109/lmag.2017.2689721openalex-snapshot

Current-Induced Dynamics of Multiple Skyrmions With Domain-Wall Pair and Skyrmion-Based Majority Gate Design

inferred← citeshttps://doi.org/10.1109/micro56248.2022.00067openalex-snapshot

pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

inferred← citeshttps://doi.org/10.1109/mwscas.2017.8053122openalex-snapshot

Leveraging spintronic devices for ultra-low power in-memory computing: Logic and neural network

inferred← citeshttps://doi.org/10.1109/tcad.2017.2774291openalex-snapshot

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption

inferred← citeshttps://doi.org/10.1109/tmag.2017.2703863openalex-snapshot

In-Memory Processing Paradigm for Bitwise Logic Operations in STT–MRAM

inferred← citeshttps://doi.org/10.1109/tmag.2018.2819959openalex-snapshot

IMCS2: Novel Device-to-Architecture Co-Design for Low-Power In-Memory Computing Platform Using Coterminous Spin Switch

inferred← citeshttps://doi.org/10.1109/tmag.2023.3288400openalex-snapshot

Circuit-Level Memory Cell Simulation of Magnetic Bloch Line Racetrack Memory

inferred← citeshttps://doi.org/10.1145/3223047openalex-snapshot

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