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pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

https://doi.org/10.1109/micro56248.2022.00067

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Outgoing claims: the papers this work cites, builds on, or argues with.

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AUGEM

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Resistive GP-SIMD Processing-In-Memory

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Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities

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ISAAC

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PRIME

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Transparent offloading and mapping (TOM)

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Neurocube

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DRAF

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Compile-time function memoization

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TETRIS

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CACTI 7

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DRISA

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CAIRO

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Google Workloads for Consumer Devices

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IMC

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CMP-PIM

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DrAcc

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Design space exploration for PIM architectures in 3D-stacked memories

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DIMA

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ParaPIM

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GraphiDe

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FloatPIM

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Duality cache for data parallel acceleration

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CoNDA

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AlignS

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LAcc

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NAPEL

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ROC

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Enabling Practical Processing in and near Memory for Data-Intensive Computing

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Sparse BD-Net

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SIMDRAM: a framework for bit-serial SIMD processing using DRAM

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A methodology and framework for software memoization of functions

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SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems

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Accelerating database analytic query workloads using an associative processor

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Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures

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Processing-in-memory: A workload-driven perspective

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Practical Mechanisms for Reducing Processor–Memory Data Movement in Modern Workloads

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Research Problems and Opportunities in Memory Systems

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Processing in 3D memories to speed up operations on complex data structures

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Memristive devices for computation-in-memory

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Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory

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GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM

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PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment

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