On the public citation graph
Band-Pass Prefetching
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s10766-013-0278-1openalex-snapshot
BADCO: Behavioral Application-Dependent Superscalar Core Models
inferredcites →https://doi.org/10.1109/c-m.1978.218016openalex-snapshot
Sequential Program Prefetching in Memory Hierarchies
inferredcites →https://doi.org/10.1109/hpca.2004.10030openalex-snapshot
Data Cache Prefetching Using a Global History Buffer
inferredcites →https://doi.org/10.1109/hpca.2007.346185openalex-snapshot
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers
inferredcites →https://doi.org/10.1109/hpca.2009.4798282openalex-snapshot
Feedback mechanisms for improving probabilistic memory prefetching
inferredcites →https://doi.org/10.1109/hpca.2014.6835971openalex-snapshot
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers
inferredcites →https://doi.org/10.1109/hpca.2015.7056020openalex-snapshot
Increasing multicore system efficiency through intelligent bandwidth shifting
inferredcites →https://doi.org/10.1109/hpca.2016.7446087openalex-snapshot
Best-offset hardware prefetching
inferredcites →https://doi.org/10.1109/icpp.2003.1240591openalex-snapshot
A hardware-based cache pollution filtering mechanism for aggressive prefetches
inferredcites →https://doi.org/10.1109/iiswc.2013.6704665openalex-snapshot
Characterizing multi-threaded applications for designing sharing-aware last-level cache replacement policies
inferredcites →https://doi.org/10.1109/ispass.2001.990695openalex-snapshot
Balancing thoughput and fairness in SMT processors
inferredcites →https://doi.org/10.1109/micro.2006.32openalex-snapshot
Memory Prefetching Using Adaptive Stream Detection
inferredcites →https://doi.org/10.1109/micro.2008.4771791openalex-snapshot
Prefetch-Aware DRAM Controllers
inferredcites →https://doi.org/10.1109/micro.2008.4771801openalex-snapshot
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
inferredcites →https://doi.org/10.1109/pact20333.2013openalex-snapshot
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques
inferredcites →https://doi.org/10.1109/samos.2012.6404158openalex-snapshot
BADCO: Behavioral Application-Dependent Superscalar Core model
inferredcites →https://doi.org/10.1109/sbac-pad.2012.27openalex-snapshot
CSHARP: Coherence and SHaring Aware Cache Replacement Policies for Parallel Applications
inferredcites →https://doi.org/10.1109/tc.2016.2547392openalex-snapshot
SPAC:A Synergistic Prefetcher Aggressiveness Controller for Multi-core Systems
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1542275.1542349openalex-snapshot
Access map pattern matching for data cache prefetch
inferredcites →https://doi.org/10.1145/1669112.1669154openalex-snapshot
Coordinated control of multiple prefetchers in multi-core systems
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/191995.192014openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1145/192007.192014openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1145/1993744.1993749openalex-snapshot
Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors
inferredcites →https://doi.org/10.1145/2000064.2000081openalex-snapshot
Prefetch-aware shared resource management for multi-core systems
inferredcites →https://doi.org/10.1145/2304576.2304614openalex-snapshot
Unified memory optimizing architecture
inferredcites →https://doi.org/10.1145/264107.264207openalex-snapshot
Prefetching using Markov predictors
inferredcites →https://doi.org/10.1145/2677956openalex-snapshot
Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks
inferredcites →https://doi.org/10.1145/2830772.2830793openalex-snapshot
Efficiently prefetching complex address patterns
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/325164.325162openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1145/379240.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferredcites →https://doi.org/10.1145/384286.264207openalex-snapshot
Prefetching using Markov predictors
inferredcites →https://doi.org/10.1147/jrd.2011.2127330openalex-snapshot
IBM POWER7 multicore server processor
inferredcites →https://doi.org/10.5555/2523721.2523774openalex-snapshot
TCPT: thread criticality-driven prefetcher throttling
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-023-05078-6openalex-snapshot
A prefetch control strategy based on improved hill-climbing method in asymmetric multi-core architecture
inferred← citeshttps://doi.org/10.1007/s11227-024-05938-9openalex-snapshot
RL-CoPref: a reinforcement learning-based coordinated prefetching controller for multiple prefetchers
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102334openalex-snapshot
SSD internal cache management policies: A survey
inferred← citeshttps://doi.org/10.1109/apccas60141.2023.00035openalex-snapshot
Reinforcement Learning Based Prefetch-Control Mechanism
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00025openalex-snapshot
To Cross, or Not to Cross Pages for Prefetching?
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408454openalex-snapshot
I-POP: Ignite Positive Prefetchers
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys60770.2023.00092openalex-snapshot
A Fairness-Aware Prefetching Mechanism based on Reinforcement Learning for Multi-Core Systems
inferred← citeshttps://doi.org/10.1109/ipdps.2019.00103openalex-snapshot
Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance
inferred← citeshttps://doi.org/10.1109/lca.2026.3720239openalex-snapshot
Pascal: Admission Control for Prefetching in Bandwidth-Constrained Multicore Systems
inferred← citeshttps://doi.org/10.70675/22db70b0z0f98z4fbez90cezf8c8729e2ea5openalex-snapshot
Compressed cache layout aware prefetching
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