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Memory Prefetching Using Adaptive Stream Detection
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.381947openalex-snapshot
Effective hardware-based data prefetching for high-performance processors
inferredcites →https://doi.org/10.1109/c-m.1978.218016openalex-snapshot
Sequential Program Prefetching in Memory Hierarchies
inferredcites →https://doi.org/10.1109/hpca.1996.501191openalex-snapshot
Distributed prefetch-buffer/cache design for high performance memory systems
inferredcites →https://doi.org/10.1109/hpca.1999.744334openalex-snapshot
Impulse: building a smarter memory controller
inferredcites →https://doi.org/10.1109/hpca.2001.903272openalex-snapshot
Reducing DRAM latencies with an integrated memory hierarchy design
inferredcites →https://doi.org/10.1109/hpca.2004.10010openalex-snapshot
Accurate and Complexity-Effective Spatial Pattern Prediction
inferredcites →https://doi.org/10.1109/hpca.2004.10030openalex-snapshot
Data Cache Prefetching Using a Global History Buffer
inferredcites →https://doi.org/10.1109/iccd.2001.955014openalex-snapshot
Filtering superfluous prefetches using density vectors
inferredcites →https://doi.org/10.1109/isca.1994.288164openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1109/isca.1998.694794openalex-snapshot
Exploiting spatial locality in data caches using spatial footprints
inferredcites →https://doi.org/10.1109/isca.2002.1003576openalex-snapshot
Using a user-level memory thread for correlation prefetching
inferredcites →https://doi.org/10.1109/micro.1997.645797openalex-snapshot
Run-time spatial locality detection and optimization
inferredcites →https://doi.org/10.1109/micro.2004.4openalex-snapshot
Adaptive History-Based Memory Schedulers
inferredcites →https://doi.org/10.1109/mm.2004.1289290openalex-snapshot
IBM power5 chip: a dual-core multithreaded processor
inferredcites →https://doi.org/10.1109/mm.2005.6openalex-snapshot
Data Cache Prefetching Using a Global History Buffer
inferredcites →https://doi.org/10.1109/mm.2006.1openalex-snapshot
Adaptive History-Based Memory Schedulers for Modern Processors
inferredcites →https://doi.org/10.1109/tc.2003.1183943openalex-snapshot
A decoupled predictor-directed stream prefetching architecture
inferredcites →https://doi.org/10.1145/191995.192014openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1145/264107.264156openalex-snapshot
Memory-system design considerations for dynamically-scheduled processors
inferredcites →https://doi.org/10.1145/264107.264207openalex-snapshot
Prefetching using Markov predictors
inferredcites →https://doi.org/10.1145/279358.279404openalex-snapshot
Exploiting spatial locality in data caches using spatial footprints
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/325164.325162openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1145/545214.545235openalex-snapshot
Using a user-level memory thread for correlation prefetching
inferredcites →https://doi.org/10.1145/996566.996749openalex-snapshot
Design and implementation of the POWER5™ microprocessor
inferredcites →https://doi.org/10.1177/109434209100500306openalex-snapshot
The NAS Parallel Benchmarks
inferredcites →https://doi.org/10.5555/266800.266806openalex-snapshot
Run-time spatial locality detection and optimization
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.5011openalex-snapshot
Adaptive TB‐LMI: An efficient memory controller and scheduler design
inferred← citeshttps://doi.org/10.1007/978-3-031-01734-6openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.1007/978-3-031-01743-8openalex-snapshot
A Primer on Hardware Prefetching
inferred← citeshttps://doi.org/10.1007/978-3-540-85451-7_36openalex-snapshot
Low-Cost Adaptive Data Prefetching
inferred← citeshttps://doi.org/10.1007/978-3-642-23400-2_29openalex-snapshot
Bandwidth Constrained Coordinated HW/SW Prefetching for Multicores
inferred← citeshttps://doi.org/10.1007/s11227-009-0348-8openalex-snapshot
Enabling adaptive live streaming in P2P multipath networks
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.03.010openalex-snapshot
Design of write merging and read prefetching buffer in DRAM controller for embedded processor
inferred← citeshttps://doi.org/10.1109/access.2022.3195046openalex-snapshot
A Cross-Prefetcher Schedule Optimization Methodology
inferred← citeshttps://doi.org/10.1109/access.2026.3659222openalex-snapshot
A Low-Cost Multi-Objective Cache Prefetcher for Complex and Irregular Memory Access Patterns
inferred← citeshttps://doi.org/10.1109/aspdac.2011.5722175openalex-snapshot
Template-based memory access engine for accelerators in SoCs
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11132724openalex-snapshot
NVR: Vector Runahead on NPUs for Sparse Memory Access
inferred← citeshttps://doi.org/10.1109/dsd60849.2023.00057openalex-snapshot
Utilizing Prefetch Buffers for Iterative Graph Applications
inferred← citeshttps://doi.org/10.1109/hipc.2017.00018openalex-snapshot
Last Level Collective Hardware Prefetching For Data-Parallel Applications
inferred← citeshttps://doi.org/10.1109/hpca.2007.346185openalex-snapshot
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798282openalex-snapshot
Feedback mechanisms for improving probabilistic memory prefetching
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749755openalex-snapshot
Dynamically Specialized Datapaths for energy efficient computing
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835971openalex-snapshot
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056020openalex-snapshot
Increasing multicore system efficiency through intelligent bandwidth shifting
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446087openalex-snapshot
Best-offset hardware prefetching
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00024openalex-snapshot
Gaze into the Pattern: Characterizing Spatial Patterns with Internal Temporal Correlations for Hardware Prefetching
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00026openalex-snapshot
Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00041openalex-snapshot
SpecLock: Speculative Lock Forwarding
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00048openalex-snapshot
APAC: An Accurate and Adaptive Prefetch Framework with Concurrent Memory Access Analysis
inferred← citeshttps://doi.org/10.1109/icnc.2011.26openalex-snapshot
CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection
inferred← citeshttps://doi.org/10.1109/iiswc.2008.4636087openalex-snapshot
Parallelization and characterization of SIFT on multi-core systems
inferred← citeshttps://doi.org/10.1109/ipdps.2019.00103openalex-snapshot
Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance
inferred← citeshttps://doi.org/10.1109/isca.2018.00018openalex-snapshot
Division of Labor: A More Effective Approach to Prefetching
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00146openalex-snapshot
ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00181openalex-snapshot
Optimizing Spatial Data Structure with Near-Cache Acceleration by Exploiting Physical Locality
inferred← citeshttps://doi.org/10.1109/ispass.2011.5762710openalex-snapshot
Characterization and dynamic mitigation of intra-application cache interference
inferred← citeshttps://doi.org/10.1109/ispass.2012.6189222openalex-snapshot
Performance analysis of thread mappings with a holistic view of the hardware resources
inferred← citeshttps://doi.org/10.1109/ispdc.2009.14openalex-snapshot
Understanding the Memory Behavior of Emerging Multi-core Workloads
inferred← citeshttps://doi.org/10.1109/lca.2014.2298412openalex-snapshot
Leveraging Non-Volatile Storage to Achieve Versatile Cache Optimizations
inferred← citeshttps://doi.org/10.1109/lca.2025.3640965openalex-snapshot
CrossFetch: A Prefetching Scheme for Cross-Page Prefetching in the Physical Address Space
inferred← citeshttps://doi.org/10.1109/mcsoc.2015.13openalex-snapshot
Adaptive Time-Based Least Memory Intensive Scheduling
inferred← citeshttps://doi.org/10.1109/micro.2008.4771791openalex-snapshot
Prefetch-Aware DRAM Controllers
inferred← citeshttps://doi.org/10.1109/micro.2016.7783763openalex-snapshot
Path confidence based lookahead prefetching
inferred← citeshttps://doi.org/10.1109/pact.2013.6618825openalex-snapshot
Automatic vectorization of tree traversals
inferred← citeshttps://doi.org/10.1109/sbac-pad.2014.19openalex-snapshot
Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level
inferred← citeshttps://doi.org/10.1109/sbac-pad55451.2022.00028openalex-snapshot
Characterizing Prefetchers using CacheObserver
inferred← citeshttps://doi.org/10.1109/tc.2010.214openalex-snapshot
Prefetch-Aware Memory Controllers
inferred← citeshttps://doi.org/10.1109/tc.2020.2980230openalex-snapshot
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption
inferred← citeshttps://doi.org/10.1109/tc.2021.3065909openalex-snapshot
Practical Temporal Prefetching With Compressed On-Chip Metadata
inferred← citeshttps://doi.org/10.1109/tcad.2016.2582872openalex-snapshot
Achieving Versatile and Simultaneous Cache Optimizations With Nonvolatile SRAM
inferred← citeshttps://doi.org/10.1109/tpds.2019.2912573openalex-snapshot
LPM: A Systematic Methodology for Concurrent Data Access Pattern Optimization from a Matching Perspective
inferred← citeshttps://doi.org/10.1109/tpds.2020.3044856openalex-snapshot
Memory-Side Prefetching Scheme Incorporating Dynamic Page Mode in 3D-Stacked DRAM
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2420315openalex-snapshot
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching
inferred← citeshttps://doi.org/10.1142/s0218126612400026openalex-snapshot
THE INTERACTION AND RELATIVE EFFECTIVENESS OF HARDWARE AND SOFTWARE DATA PREFETCH
inferred← citeshttps://doi.org/10.1145/1555754.1555766openalex-snapshot
Spatio-temporal memory streaming
inferred← citeshttps://doi.org/10.1145/1555815.1555766openalex-snapshot
Spatio-temporal memory streaming
inferred← citeshttps://doi.org/10.1145/1654059.1654116openalex-snapshot
Machine learning-based prefetch optimization for data center applications
inferred← citeshttps://doi.org/10.1145/1669112.1669155openalex-snapshot
Improving memory bank-level parallelism in the presence of prefetching
inferred← citeshttps://doi.org/10.1145/2133382.2133384openalex-snapshot
When Prefetching Works, When It Doesn’t, and Why
inferred← citeshttps://doi.org/10.1145/2540708.2540730openalex-snapshot
Linearizing irregular memory accesses for improved correlated prefetching
inferred← citeshttps://doi.org/10.1145/2593069.2593128openalex-snapshot
Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes
inferred← citeshttps://doi.org/10.1145/2659787.2659824openalex-snapshot
WCET Preserving Hardware Prefetch for Many-Core Real-Time Systems
inferred← citeshttps://doi.org/10.1145/2830772.2830793openalex-snapshot
Efficiently prefetching complex address patterns
inferred← citeshttps://doi.org/10.1145/2830772.2830816openalex-snapshot
Self-contained, accurate precomputation prefetching
inferred← citeshttps://doi.org/10.1145/2907071openalex-snapshot
A Survey of Recent Prefetching Techniques for Processor Caches
inferred← citeshttps://doi.org/10.1145/3240302.3240314openalex-snapshot
Tackling memory access latency through DRAM row management
inferred← citeshttps://doi.org/10.1145/3243176.3243181openalex-snapshot
Near-side prefetch throttling
inferred← citeshttps://doi.org/10.1145/3312740openalex-snapshot
Evaluation of Hardware Data Prefetchers on Server Processors
inferred← citeshttps://doi.org/10.1145/3352460.3358300openalex-snapshot
Temporal Prefetching Without the Off-Chip Metadata
inferred← citeshttps://doi.org/10.1145/3373376.3378498openalex-snapshot
Classifying Memory Access Patterns for Prefetching
inferred← citeshttps://doi.org/10.1145/3422575.3422804openalex-snapshot
PreFAM: Understanding the Impact of Prefetching in Fabric-Attached Memory Architectures
inferred← citeshttps://doi.org/10.1145/3445814.3446752openalex-snapshot
A hierarchical neural model of data prefetching
inferred← citeshttps://doi.org/10.1145/3503222.3507745openalex-snapshot
CRISP: critical slice prefetching
inferred← citeshttps://doi.org/10.1145/3528416.3530236openalex-snapshot
Fine-grained address segmentation for attention-based variable-degree prefetching
inferred← citeshttps://doi.org/10.1145/3570304openalex-snapshot
Puppeteer: A Random Forest Based Manager for Hardware Prefetchers Across the Memory Hierarchy
inferred← citeshttps://doi.org/10.1145/3613424.3623780openalex-snapshot
Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-Making
inferred← citeshttps://doi.org/10.1145/3620665.3640396openalex-snapshot
RPG 2 : Robust Profile-Guided Runtime Prefetch Generation
inferred← citeshttps://doi.org/10.1145/3695053.3731070openalex-snapshot
Profile-Guided Temporal Prefetching
inferred← citeshttps://doi.org/10.11606/d.3.2011.tde-31082011-163312openalex-snapshot
Power Laws na modelagem de caches de microprocessadores.
inferred← citeshttps://doi.org/10.1184/r1/6723512openalex-snapshot
Techniques for Shared Resource Management in Systems with Throughput Processors
inferred← citeshttps://doi.org/10.1587/transinf.e95.d.2928openalex-snapshot
Using Cacheline Reuse Characteristics for Prefetcher Throttling
inferred← citeshttps://doi.org/10.2200/s00365ed1v01y201105cac017openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.2200/s00581ed1v01y201405cac028openalex-snapshot
A Primer on Hardware Prefetching
inferred← citeshttps://doi.org/10.23860/diss-avus-mustafa-2019openalex-snapshot
SOFTWARE SUPPORT FOR HARDWARE PREDICTORS
inferred← citeshttps://doi.org/10.25046/aj070613openalex-snapshot
Extended Buffer-referred Prefetching to Leverage Prefetch Coverage
inferred← citeshttps://doi.org/10.2991/icmt-13.2013.200openalex-snapshot
Smart-Eyes: a FPGA-based smart camera platform with efficient multi-port memory controller
inferred← citeshttps://doi.org/10.3390/electronics14142811openalex-snapshot
A Generalized Optimization Scheme for Memory-Side Prefetching to Enhance System Performance
inferred← citeshttps://doi.org/10.4304/jmm.9.7.926-933openalex-snapshot
Cache Performance Optimization for SoC Vedio Applications
inferred← citeshttps://doi.org/10.48550/arxiv.1106.2568openalex-snapshot
HMTT: A Hybrid Hardware/Software Tracing System for Bridging Memory Trace's Semantic Gap
inferred← citeshttps://doi.org/10.48550/arxiv.1804.11043openalex-snapshot
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems
inferred← citeshttps://doi.org/10.5555/1950815.1950857openalex-snapshot
Template-based memory access engine for accelerators in SoCs
inferred← citeshttps://doi.org/10.5555/2523721.2523761openalex-snapshot
Meeting midway: improving CMP performance with memory-side prefetching
inferred← citeshttps://doi.org/10.5555/3195638.3195711openalex-snapshot
Path confidence based lookahead prefetching
inferred← citeshttps://doi.org/10.5821/dissertation-2117-105576openalex-snapshot
Improving the efficiency of multicore systems through software and hardware cooperation
inferred← citeshttps://doi.org/10.5821/dissertation-2117-413894openalex-snapshot
Hardware knob coordination in multi-threaded systems
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