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An Out-of-Order Load-Store Queue for Spatial Computing
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/43.945302openalex-snapshot
Theory of latency-insensitive design
inferredcites →https://doi.org/10.1109/async.2002.1000291openalex-snapshot
Synchronous interlocked pipelines
inferredcites →https://doi.org/10.1109/fccm.2015.31openalex-snapshot
Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS
inferredcites →https://doi.org/10.1109/fpt.2013.6718409openalex-snapshot
Efficient methods for out-of-order load/store execution for high-performance soft processors
inferredcites →https://doi.org/10.1109/iccad.2008.4681612openalex-snapshot
Correct-by-construction microarchitectural pipelining
inferredcites →https://doi.org/10.1109/isca.2008.10openalex-snapshot
A Two-Level Load/Store Queue Based on Execution Locality
inferredcites →https://doi.org/10.1109/ispass.2005.1430572openalex-snapshot
Dataflow: A Complement to Superscalar
inferredcites →https://doi.org/10.1145/1146909.1147077openalex-snapshot
Synthesis of synchronous elastic architectures
inferredcites →https://doi.org/10.1145/2429384openalex-snapshot
Proceedings of the International Conference on Computer-Aided Design
inferredcites →https://doi.org/10.1145/2463209.2488796openalex-snapshot
Runtime dependency analysis for loop pipelining in high-level synthesis
inferredcites →https://doi.org/10.1145/2593069.2593143openalex-snapshot
Flushing-Enabled Loop Pipelining for High-Level Synthesis
inferredcites →https://doi.org/10.1145/2656106.2656109openalex-snapshot
A low-cost memory interface for high-throughput accelerators
inferredcites →https://doi.org/10.1145/2754930openalex-snapshot
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures
inferredcites →https://doi.org/10.1145/2966986.2967077openalex-snapshot
Synthesis of statically analyzable accelerator networks from sequential programs
inferredcites →https://doi.org/10.1145/3020078.3021754openalex-snapshot
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis
inferredcites →https://doi.org/10.1184/r1/6608207openalex-snapshot
Optimizing Memory Accesses For Spatial Computation
inferredcites →https://doi.org/10.1184/r1/6608339openalex-snapshot
Pegasus: An Efficient Intermediate Representation
inferredcites →https://doi.org/10.5555/1715759.1715781openalex-snapshot
Bounded dataflow networks and latency-insensitive circuits
inferredcites →https://doi.org/10.5555/956417.956555openalex-snapshot
Reducing design complexity of the load/store queue
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10470-021-01885-0openalex-snapshot
Fast DSE of reconfigurable accelerator systems via ensemble machine learning
inferred← citeshttps://doi.org/10.1109/acssc.2017.8335150openalex-snapshot
From C to elastic circuits
inferred← citeshttps://doi.org/10.1109/acssc.2017.8335152openalex-snapshot
Enabling adaptive loop pipelining in high-level synthesis
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133111openalex-snapshot
PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fccm.2018.00027openalex-snapshot
LegUp-NoC: High-Level Synthesis of Loops with Indirect Addressing
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00031openalex-snapshot
Probabilistic Scheduling in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fccm53951.2022.9786096openalex-snapshot
Dynamic C-Slow Pipelining for HLS
inferred← citeshttps://doi.org/10.1109/fccm57271.2023.00048openalex-snapshot
Dynamically Scheduled Memory Operations in Static High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00045openalex-snapshot
Dynamic Inter-Block Scheduling for HLS
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00063openalex-snapshot
A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits
inferred← citeshttps://doi.org/10.1109/fpl60245.2023.00009openalex-snapshot
Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fpl64840.2024.00024openalex-snapshot
Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fpl64840.2024.00025openalex-snapshot
Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323796openalex-snapshot
Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00031openalex-snapshot
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs
inferred← citeshttps://doi.org/10.1109/icfpt56656.2022.9974262openalex-snapshot
Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/icfpt59805.2023.00018openalex-snapshot
A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/mcas.2021.3071631openalex-snapshot
Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits
inferred← citeshttps://doi.org/10.1109/tc.2023.3292590openalex-snapshot
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets
inferred← citeshttps://doi.org/10.1109/tcad.2021.3065902openalex-snapshot
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/tcad.2021.3105574openalex-snapshot
From C/C++ Code to High-Performance Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3174243.3174264openalex-snapshot
Dynamically Scheduled High-level Synthesis
inferred← citeshttps://doi.org/10.1145/3373087.3375297openalex-snapshot
Combining Dynamic & Static Scheduling in High-level Synthesis
inferred← citeshttps://doi.org/10.1145/3469660openalex-snapshot
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects
inferred← citeshttps://doi.org/10.1145/3477053openalex-snapshot
Buffer Placement and Sizing for High-Performance Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3490422.3502362openalex-snapshot
Finding and Finessing Static Islands in Dynamically Scheduled Circuits
inferred← citeshttps://doi.org/10.1145/3543622.3573050openalex-snapshot
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3597614openalex-snapshot
Resource Sharing in Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3617232.3624850openalex-snapshot
HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3626202.3637556openalex-snapshot
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3626202.3637570openalex-snapshot
Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing
inferred← citeshttps://doi.org/10.1145/3656420openalex-snapshot
Wavefront Threading Enables Effective High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3669940.3707273openalex-snapshot
CRUSH: A Cr edit-Based Approach for Functional U nit Sh aring in Dynamically Scheduled HLS
inferred← citeshttps://doi.org/10.1145/3706628.3708871openalex-snapshot
Dynamic Loop Fusion in High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3748173.3779204openalex-snapshot
Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS
inferred← citeshttps://doi.org/10.1145/3779212.3790166openalex-snapshot
Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits
inferred← citeshttps://doi.org/10.23919/date64628.2025.10993073openalex-snapshot
PreVV: Eliminating Store Queue via Premature Value Validation for Dataflow Circuit on FPGA
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