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Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-01857-7_47openalex-snapshot
A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing
inferredcites →https://doi.org/10.1007/978-3-319-26408-0_8openalex-snapshot
Source-to-Source Optimization for HLS
inferredcites →https://doi.org/10.1007/978-3-540-78610-8_30openalex-snapshot
PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications
inferredcites →https://doi.org/10.1007/978-3-642-03034-5_13openalex-snapshot
Domain-Specific Language for HW/SW Co-design for FPGAs
inferredcites →https://doi.org/10.1016/j.jpdc.2018.02.012openalex-snapshot
Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilation
inferredcites →https://doi.org/10.1016/j.mejo.2013.02.021openalex-snapshot
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
inferredcites →https://doi.org/10.1023/a:1015341305426openalex-snapshot
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
inferredcites →https://doi.org/10.1023/b:numa.0000049462.70970.b6openalex-snapshot
Affine Arithmetic: Concepts and Applications
inferredcites →https://doi.org/10.1109/access.2019.2957819openalex-snapshot
FPGA Based Real-Time Implementation of Online EMD With Fixed Point Architecture
inferredcites →https://doi.org/10.1109/access.2020.3024098openalex-snapshot
Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains
inferredcites →https://doi.org/10.1109/acssc.2017.8335152openalex-snapshot
Enabling adaptive loop pipelining in high-level synthesis
inferredcites →https://doi.org/10.1109/asap.2013.6567545openalex-snapshot
Aspect driven compilation for dataflow designs
inferredcites →https://doi.org/10.1109/asap.2019.00013openalex-snapshot
Understanding Performance Gains of Accelerator-Rich Architectures
inferredcites →https://doi.org/10.1109/dac.2018.8465940openalex-snapshot
Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture
inferredcites →https://doi.org/10.1109/fccm.2007.19openalex-snapshot
Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-Chip
inferredcites →https://doi.org/10.1109/fccm.2010.32openalex-snapshot
Automated Precision Analysis: A Polynomial Algebraic Approach
inferredcites →https://doi.org/10.1109/fccm.2012.13openalex-snapshot
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems
inferredcites →https://doi.org/10.1109/fccm.2012.25openalex-snapshot
ZUMA: An Open FPGA Overlay Architecture
inferredcites →https://doi.org/10.1109/fccm.2012.55openalex-snapshot
VENICE: A Compact Vector Processor for FPGA Applications
inferredcites →https://doi.org/10.1109/fccm.2015.31openalex-snapshot
Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS
inferredcites →https://doi.org/10.1109/fccm.2018.00011openalex-snapshot
ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA
inferredcites →https://doi.org/10.1109/fccm.2018.00018openalex-snapshot
ReBNet: Residual Binarized Neural Network
inferredcites →https://doi.org/10.1109/fccm.2018.00022openalex-snapshot
Hot & Spicy: Improving Productivity with Python and HLS for FPGAs
inferredcites →https://doi.org/10.1109/fccm.2018.00027openalex-snapshot
LegUp-NoC: High-Level Synthesis of Loops with Indirect Addressing
inferredcites →https://doi.org/10.1109/fccm.2018.00028openalex-snapshot
Latte: Locality Aware Transformation for High-Level Synthesis
inferredcites →https://doi.org/10.1109/fccm.2018.00029openalex-snapshot
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
inferredcites →https://doi.org/10.1109/fccm.2018.00030openalex-snapshot
RapidWright: Enabling Custom Crafted Implementations for FPGAs
inferredcites →https://doi.org/10.1109/fccm.2019.00018openalex-snapshot
RapidRoute: Fast Assembly of Communication Structures for FPGA Overlays
inferredcites →https://doi.org/10.1109/fccm.2019.00020openalex-snapshot
LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure
inferredcites →https://doi.org/10.1109/fccm.2019.00027openalex-snapshot
Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU
inferredcites →https://doi.org/10.1109/fccm.2019.00028openalex-snapshot
Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform
inferredcites →https://doi.org/10.1109/fccm.2019.00033openalex-snapshot
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations
inferredcites →https://doi.org/10.1109/fccm.2019.00034openalex-snapshot
SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional Computing
inferredcites →https://doi.org/10.1109/fccm48280.2020.00020openalex-snapshot
Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs
inferredcites →https://doi.org/10.1109/fccm48280.2020.00033openalex-snapshot
Hierarchical Modelling of Generators in Design-Space Exploration
inferredcites →https://doi.org/10.1109/fpga.1993.279483openalex-snapshot
Spyder: a reconfigurable VLIW processor using FPGAs
inferredcites →https://doi.org/10.1109/fpga.1994.315584openalex-snapshot
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines
inferredcites →https://doi.org/10.1109/fpl.2007.4380730openalex-snapshot
Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems
inferredcites →https://doi.org/10.1109/fpl.2013.6645550openalex-snapshot
Bambu: A modular framework for the high level synthesis of memory-intensive applications
inferredcites →https://doi.org/10.1109/fpl.2013.6645597openalex-snapshot
Runtime assertions and exceptions for streaming systems
inferredcites →https://doi.org/10.1109/fpl.2014.6927481openalex-snapshot
A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures
inferredcites →https://doi.org/10.1109/fpl.2015.7293956openalex-snapshot
Hoplite: Building austere overlay NoCs for FPGAs
inferredcites →https://doi.org/10.1109/fpl.2016.7577357openalex-snapshot
FPGA-based accelerator design from a domain-specific language
inferredcites →https://doi.org/10.1109/fpl.2016.7577358openalex-snapshot
Model-based optimization of High Level Synthesis directives
inferredcites →https://doi.org/10.1109/fpl.2018.00011openalex-snapshot
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model
inferredcites →https://doi.org/10.1109/fpl.2018.00016openalex-snapshot
FBNA: A Fully Binarized Neural Network Accelerator
inferredcites →https://doi.org/10.1109/fpl.2018.00047openalex-snapshot
Case for Fast FPGA Compilation Using Partial Reconfiguration
inferredcites →https://doi.org/10.1109/fpl.2018.00054openalex-snapshot
Multi-fidelity Optimization for High-Level Synthesis Directives
inferredcites →https://doi.org/10.1109/fpl.2018.00077openalex-snapshot
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration
inferredcites →https://doi.org/10.1109/fpl.2019.00020openalex-snapshot
On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL-Based FPGAs
inferredcites →https://doi.org/10.1109/fpl.2019.00059openalex-snapshot
Specializing FGPU for Persistent Deep Learning
inferredcites →https://doi.org/10.1109/fpt.2013.6718365openalex-snapshot
From software threads to parallel hardware in high-level synthesis for FPGAs
inferredcites →https://doi.org/10.1109/fpt.2017.8280122openalex-snapshot
HopliteRT: An efficient FPGA NoC for real-time applications
inferredcites →https://doi.org/10.1109/hpca.2016.7446050openalex-snapshot
TABLA: A unified template-based framework for accelerating statistical machine learning
inferredcites →https://doi.org/10.1109/icac.2018.00021openalex-snapshot
A Domain-Specific Language for Autonomic Managers in FPGA Reconfigurable Architectures
inferredcites →https://doi.org/10.1109/icfpt47387.2019.00026openalex-snapshot
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks
inferredcites →https://doi.org/10.1109/imsna.2013.6743419openalex-snapshot
Application of multi-core parallel computing in FPGA placement
inferredcites →https://doi.org/10.1109/isca.2018.00012openalex-snapshot
A Configurable Cloud-Scale DNN Processor for Real-Time AI
inferredcites →https://doi.org/10.1109/iscas.2014.6865091openalex-snapshot
A design approach to automatically synthesize ANSI-C assertions during High-Level Synthesis of hardware accelerators
inferredcites →https://doi.org/10.1109/isqed.2007.41openalex-snapshot
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
inferredcites →https://doi.org/10.1109/jproc.2018.2876372openalex-snapshot
Customizable Computing—From Single Chip to Datacenters
inferredcites →https://doi.org/10.1109/mdat.2017.2741459openalex-snapshot
CPU-FPGA Coscheduling for Big Data Applications
inferredcites →https://doi.org/10.1109/mdat.2017.2746638openalex-snapshot
Exploiting Execution Dynamics in Timing Analysis Using Job Sequences
inferredcites →https://doi.org/10.1109/mdt.2011.44openalex-snapshot
Designing Custom Arithmetic Data Paths with FloPoCo
inferredcites →https://doi.org/10.1109/micro.2018.00014openalex-snapshot
An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware
inferredcites →https://doi.org/10.1109/mm.2020.2998435openalex-snapshot
SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs
inferredcites →https://doi.org/10.1109/mssc.2018.2822862openalex-snapshot
Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology: This Paper Reflects on How Moore's Law Has Driven the Design of FPGAs Through Three Epochs: the Age of Invention, the Age of Expansion, and the Age of Accumulation
inferredcites →https://doi.org/10.1109/reconfig.2011.27openalex-snapshot
Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition
inferredcites →https://doi.org/10.1109/reconfig.2015.7393356openalex-snapshot
Scalable analytic placement for FPGA on GPGPU
inferredcites →https://doi.org/10.1109/tcad.2006.873887openalex-snapshot
Accuracy-Guaranteed Bit-Width Optimization
inferredcites →https://doi.org/10.1109/tcad.2006.887921openalex-snapshot
Exploration and Customization of FPGA-Based Soft Processors
inferredcites →https://doi.org/10.1109/tcad.2011.2110592openalex-snapshot
High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1109/tcad.2012.2228270openalex-snapshot
Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis
inferredcites →https://doi.org/10.1109/tcad.2013.2277978openalex-snapshot
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic
inferredcites →https://doi.org/10.1109/tcad.2015.2488491openalex-snapshot
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
inferredcites →https://doi.org/10.1109/tcad.2015.2513673openalex-snapshot
A Survey and Evaluation of FPGA High-Level Synthesis Tools
inferredcites →https://doi.org/10.1109/tcad.2016.2565204openalex-snapshot
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits
inferredcites →https://doi.org/10.1109/tcad.2017.2783363openalex-snapshot
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis
inferredcites →https://doi.org/10.1109/tcad.2017.2785257openalex-snapshot
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/tcad.2019.2901243openalex-snapshot
ParRA: A Shared Memory Parallel FPGA Router Using Hybrid Partitioning Approach
inferredcites →https://doi.org/10.1109/tcad.2019.2930577openalex-snapshot
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators
inferredcites →https://doi.org/10.1109/tcad.2019.2954472openalex-snapshot
QuantHD: A Quantization Framework for Hyperdimensional Computing
inferredcites →https://doi.org/10.1109/tcad.2020.2970597openalex-snapshot
FLASH: Fast, Parallel, and Accurate Simulator for HLS
inferredcites →https://doi.org/10.1109/tcad.2020.3003843openalex-snapshot
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
inferredcites →https://doi.org/10.1109/tcad.2020.3012750openalex-snapshot
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis
inferredcites →https://doi.org/10.1109/tcad.2020.3012866openalex-snapshot
Toward Speculative Loop Pipelining for High-Level Synthesis
inferredcites →https://doi.org/10.1109/tcsvt.2014.2360030openalex-snapshot
Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs
inferredcites →https://doi.org/10.1109/tpds.2015.2394802openalex-snapshot
HIPAcc: A Domain-Specific Language and Compiler for Image Processing
inferredcites →https://doi.org/10.1109/tpds.2019.2910068openalex-snapshot
HitGraph: High-throughput Graph Processing Framework on FPGA
inferredcites →https://doi.org/10.1109/tpds.2020.3035787openalex-snapshot
Coarse-Grained Parallel Routing With Recursive Partitioning for FPGAs
inferredcites →https://doi.org/10.1109/tpds.2020.3039409openalex-snapshot
Transformations of High-Level Synthesis Codes for High-Performance Computing
inferredcites →https://doi.org/10.1109/tvlsi.2015.2497259openalex-snapshot
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
inferredcites →https://doi.org/10.1142/s0129626412500107openalex-snapshot
POLLY — PERFORMING POLYHEDRAL OPTIMIZATIONS ON A LOW-LEVEL INTERMEDIATE REPRESENTATION
inferredcites →https://doi.org/10.1145/1088149.1088169openalex-snapshot
Facilitating the search for compositions of program transformations
inferredcites →https://doi.org/10.1145/1122501.1122502openalex-snapshot
The halfway vector disk for BRDF modeling
inferredcites →https://doi.org/10.1145/1146909.1147025openalex-snapshot
An efficient and versatile scheduling algorithm based on SDC formulation
inferredcites →https://doi.org/10.1145/1229428.1229446openalex-snapshot
Automatic mapping of nested loops to FPGAS
inferredcites →https://doi.org/10.1145/1344671.1344676openalex-snapshot
High-quality, deterministic parallel placement for FPGAs on commodity hardware
inferredcites →https://doi.org/10.1145/1344671.1344704openalex-snapshot
Vector processing as a soft-core CPU accelerator
inferredcites →https://doi.org/10.1145/1379022.1375595openalex-snapshot
A practical automatic polyhedral parallelizer and locality optimizer
inferredcites →https://doi.org/10.1145/1661438.1661443openalex-snapshot
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing
inferredcites →https://doi.org/10.1145/1929943.1929947openalex-snapshot
Automatic memory partitioning and scheduling for throughput and power optimization
inferredcites →https://doi.org/10.1145/1950413.1950445openalex-snapshot
Scalable and deterministic timing-driven parallel placement for FPGAs
inferredcites →https://doi.org/10.1145/1970353.1970355openalex-snapshot
Efficient and Deterministic Parallel Placement for FPGAs
inferredcites →https://doi.org/10.1145/2145694.2145726openalex-snapshot
A scalable approach for automated precision analysis
inferredcites →https://doi.org/10.1145/2159542.2159547openalex-snapshot
Computer Generation of Hardware for Linear Digital Signal Processing Transforms
inferredcites →https://doi.org/10.1145/2435264.2435273openalex-snapshot
Polyhedral-based data reuse optimization for configurable computing
inferredcites →https://doi.org/10.1145/2463209.2488748openalex-snapshot
Memory partitioning for multidimensional arrays in high-level synthesis
inferredcites →https://doi.org/10.1145/2463209.2488796openalex-snapshot
Runtime dependency analysis for loop pipelining in high-level synthesis
inferredcites →https://doi.org/10.1145/2554688.2554774openalex-snapshot
Soft vector processors with streaming pipelines
inferredcites →https://doi.org/10.1145/2554688.2554780openalex-snapshot
Theory and algorithm for generalized memory partitioning in high-level synthesis
inferredcites →https://doi.org/10.1145/2593069.2593143openalex-snapshot
Flushing-Enabled Loop Pipelining for High-Level Synthesis
inferredcites →https://doi.org/10.1145/2675359openalex-snapshot
Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2684746.2689063openalex-snapshot
Mapping-Aware Constrained Scheduling for LUT-Based FPGAs
inferredcites →https://doi.org/10.1145/2684746.2689087openalex-snapshot
Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs
inferredcites →https://doi.org/10.1145/2744769.2744801openalex-snapshot
Area-efficient pipelining for FPGA-targeted high-level synthesis
inferredcites →https://doi.org/10.1145/2847263.2847265openalex-snapshot
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/2847263.2847266openalex-snapshot
GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths
inferredcites →https://doi.org/10.1145/2897937.2897972openalex-snapshot
A quantitative analysis on microarchitectures of modern CPU-FPGA platforms
inferredcites →https://doi.org/10.1145/2987550.2987569openalex-snapshot
Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale
inferredcites →https://doi.org/10.1145/3007787.3001150openalex-snapshot
Automatic generation of efficient accelerators for reconfigurable hardware
inferredcites →https://doi.org/10.1145/3020078.3021734openalex-snapshot
A New Approach to Automatic Memory Banking using Trace-Based Address Mining
inferredcites →https://doi.org/10.1145/3020078.3021741openalex-snapshot
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs
inferredcites →https://doi.org/10.1145/3020078.3021749openalex-snapshot
Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling
inferredcites →https://doi.org/10.1145/3020078.3021754openalex-snapshot
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis
inferredcites →https://doi.org/10.1145/3020078.3021772openalex-snapshot
Using Vivado-HLS for Structural Design
inferredcites →https://doi.org/10.1145/3061639.3062207openalex-snapshot
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
inferredcites →https://doi.org/10.1145/3061639.3062208openalex-snapshot
Bandwidth Optimization Through On-Chip Memory Restructuring for HLS
inferredcites →https://doi.org/10.1145/3061639.3062230openalex-snapshot
Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs
inferredcites →https://doi.org/10.1145/3075620openalex-snapshot
Decoupling Data Supply from Computation for Latency-Tolerant Communication in Heterogeneous Architectures
inferredcites →https://doi.org/10.1145/3107953openalex-snapshot
Programming Heterogeneous Systems from an Image Processing DSL
inferredcites →https://doi.org/10.1145/3126525openalex-snapshot
An Out-of-Order Load-Store Queue for Spatial Computing
inferredcites →https://doi.org/10.1145/3126564openalex-snapshot
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis
inferredcites →https://doi.org/10.1145/3174243.3174260openalex-snapshot
Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform
inferredcites →https://doi.org/10.1145/3174243.3174264openalex-snapshot
Dynamically Scheduled High-level Synthesis
inferredcites →https://doi.org/10.1145/3174243.3174268openalex-snapshot
A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation
inferredcites →https://doi.org/10.1145/3204919.3204937openalex-snapshot
Early experiments using SYCL single-source modern C++ on Xilinx FPGA
inferredcites →https://doi.org/10.1145/3218603.3218615openalex-snapshot
A Fully Onchip Binarized Convolutional Neural Network FPGA Impelmentation with Accurate Inference
inferredcites →https://doi.org/10.1145/3240765.3240815openalex-snapshot
HLS-based optimization and design space exploration for applications with variable loop bounds
inferredcites →https://doi.org/10.1145/3241045openalex-snapshot
Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug
inferredcites →https://doi.org/10.1145/324133.324234openalex-snapshot
Scheduling multithreaded computations by work stealing
inferredcites →https://doi.org/10.1145/3289602.3293914openalex-snapshot
Speculative Dataflow Circuits
inferredcites →https://doi.org/10.1145/3289602.3293922openalex-snapshot
On-chip FPGA Debug Instrumentation for Machine Learning Applications
inferredcites →https://doi.org/10.1145/3289602.3293924openalex-snapshot
The P4->NetFPGA Workflow for Line-Rate Packet Processing
inferredcites →https://doi.org/10.1145/3294054openalex-snapshot
In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms
inferredcites →https://doi.org/10.1145/3296979.3192379openalex-snapshot
Spatial: a language and compiler for application accelerators
inferredcites →https://doi.org/10.1145/3373087.3375297openalex-snapshot
Combining Dynamic & Static Scheduling in High-level Synthesis
inferredcites →https://doi.org/10.1145/3373087.3375299openalex-snapshot
High-Performance FPGA Network Switch Architecture
inferredcites →https://doi.org/10.1145/3373087.3375321openalex-snapshot
End-to-End Optimization of Deep Learning Applications
inferredcites →https://doi.org/10.1145/3373376.3378491openalex-snapshot
Virtualizing FPGAs in the Cloud
inferredcites →https://doi.org/10.1145/3385412.3385974openalex-snapshot
Predictable accelerator design with time-sensitive affine types
inferredcites →https://doi.org/10.1145/3385412.3385983openalex-snapshot
Type-directed scheduling of streaming accelerators
inferredcites →https://doi.org/10.1145/3400302.3415657openalex-snapshot
Accurate operation delay prediction for FPGA HLS using graph neural networks
inferredcites →https://doi.org/10.1145/3431920.3439284openalex-snapshot
Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers through Microbenchmarking
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What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-13074-8_16openalex-snapshot
Machine Learning for Agile FPGA Design
inferred← citeshttps://doi.org/10.1007/s10766-022-00748-zopenalex-snapshot
Accelerating OCaml Programs on FPGA
inferred← citeshttps://doi.org/10.1007/s10766-025-00801-7openalex-snapshot
Programming Parallelism on FPGAs with Eclat
inferred← citeshttps://doi.org/10.1007/s13369-023-07926-2openalex-snapshot
FPGA-Based Hardware-Accelerated Design of Linear Prediction Analysis for Real-Time Speech Signal
inferred← citeshttps://doi.org/10.1016/b978-0-443-45574-2.00009-5openalex-snapshot
Distributed and shared memory concepts
inferred← citeshttps://doi.org/10.1109/access.2025.3540320openalex-snapshot
High-Level Synthesis for FPGAs—A Hardware Engineer’s Perspective
inferred← citeshttps://doi.org/10.1109/acit65614.2025.11185710openalex-snapshot
Generative AI-Assisted High-Level Design of Computer Devices: First Experience
inferred← citeshttps://doi.org/10.1109/comst.2025.3587225openalex-snapshot
Edge-Enhanced Intelligence: A Comprehensive Survey of Large Language Models and Edge-Cloud Computing Synergy
inferred← citeshttps://doi.org/10.1109/fccm53951.2022.9786123openalex-snapshot
IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS
inferred← citeshttps://doi.org/10.1109/fccm57271.2023.00013openalex-snapshot
Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs
inferred← citeshttps://doi.org/10.1109/icce62051.2024.10634722openalex-snapshot
Preserving Power Optimizations Across the High Level Synthesis of Distinct Application-Specific Circuits
inferred← citeshttps://doi.org/10.1109/icpeca60615.2024.10471036openalex-snapshot
Low-Power Design of Advanced Image Processing Algorithms under FPGA in Real-Time Applications
inferred← citeshttps://doi.org/10.1109/jssc.2024.3522355openalex-snapshot
A 28-nm Software-Defined Accelerator Chip With Circuit-Pipeline Scaling and Intrinsic Physical Unclonable Function Enabling Secure Configuration
inferred← citeshttps://doi.org/10.1109/rtcsa62462.2024.00025openalex-snapshot
Real-time Beamforming Testbed and Tracking Relay for mmWave Applications
inferred← citeshttps://doi.org/10.1109/sc41406.2024.00051openalex-snapshot
NetCL: A Unified Programming Framework for In-Network Computing
inferred← citeshttps://doi.org/10.1109/tbcas.2024.3388323openalex-snapshot
Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool With High-Accuracy and Multi-Level Parallelism
inferred← citeshttps://doi.org/10.1109/tcad.2023.3325972openalex-snapshot
Weave: Abstraction and Integration Flow for Accelerators of Generated Modules
inferred← citeshttps://doi.org/10.1145/3489517.3530681openalex-snapshot
Accelerator design with decoupled hardware customizations
inferred← citeshttps://doi.org/10.1145/3490422.3502368openalex-snapshot
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
inferred← citeshttps://doi.org/10.1145/3530775openalex-snapshot
FPGA HLS Today: Successes, Challenges, and Opportunities
inferred← citeshttps://doi.org/10.1145/3563553openalex-snapshot
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics
inferred← citeshttps://doi.org/10.1145/3593025openalex-snapshot
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration
inferred← citeshttps://doi.org/10.1145/3607888openalex-snapshot
Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis
inferred← citeshttps://doi.org/10.1145/3607888.3608962openalex-snapshot
Special Session: Machine Learning for Embedded System Design
inferred← citeshttps://doi.org/10.1145/3611643.3616318openalex-snapshot
Leveraging Hardware Probes and Optimizations for Accelerating Fuzz Testing of Heterogeneous Applications
inferred← citeshttps://doi.org/10.1145/3626202.3637563openalex-snapshot
Formal Verification of Source-to-Source Transformations for HLS
inferred← citeshttps://doi.org/10.1145/3639051openalex-snapshot
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface
inferred← citeshttps://doi.org/10.1145/3656401openalex-snapshot
Allo: A Programming Model for Composable Accelerator Design
inferred← citeshttps://doi.org/10.1145/3676849openalex-snapshot
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
inferred← citeshttps://doi.org/10.1145/3705732openalex-snapshot
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3723046openalex-snapshot
Productively Generating a High-Performance Linear Algebra Library on FPGAs
inferred← citeshttps://doi.org/10.1145/3764664openalex-snapshot
A Taxonomy of the High-Level Synthesis Ecosystem for Heterogeneous FPGA Systems
inferred← citeshttps://doi.org/10.1145/3767295.3803577openalex-snapshot
Proteus: Heterogeneous FPGA Virtualization
inferred← citeshttps://doi.org/10.11606/t.55.2023.tde-31082023-103217openalex-snapshot
Applying Rosenbrock method for solving stiff ODEs raised from the chemical reactivity of the atmosphere through heterogeneous architectures based on FPGAs
inferred← citeshttps://doi.org/10.1186/s12938-025-01393-6openalex-snapshot
Design, construction, and deployment of a multi-locus transcranial magnetic stimulation system for clinical use
inferred← citeshttps://doi.org/10.23977/curtm.2023.061719openalex-snapshot
Exploration of Teaching Reform in Programming Courses under the Background of Emerging Engineering Education
inferred← citeshttps://doi.org/10.3233/jcm-226842openalex-snapshot
Optimal FPGA memory allocation for image processing
inferred← citeshttps://doi.org/10.34218/ijcet_16_03_017openalex-snapshot
RECONFIGURABLE FPGA-BASED ACCELERATION OF RTL SIMULATION AND CO-SIMULATION FOR DATACENTER WORKLOADS
inferred← citeshttps://doi.org/10.7717/peerj-cs.3833openalex-snapshot
Design and field programmable gate array implementation of a Rossler-driven four-dimensional hyperchaotic Rossler–advanced encryption standard framework for image encryption
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