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Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs

https://doi.org/10.1145/3182183
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-319-16214-0_7openalex-snapshot
Preemptive Hardware Multitasking in ReconOS
inferredcites →https://doi.org/10.1109/fpl.2012.6339165openalex-snapshot
Bil: A tool-chain for bitstream reverse-engineering
inferredcites →https://doi.org/10.1109/jproc.2014.2386883openalex-snapshot
Reconfigurable Computing Architectures
inferredcites →https://doi.org/10.1109/les.2015.2396069openalex-snapshot
Scheduling Dynamic Hard Real-Time Task Sets on Fully and Partially Reconfigurable Platforms
inferredcites →https://doi.org/10.1109/les.2017.2714844openalex-snapshot
CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems
inferredcites →https://doi.org/10.1109/rtss.2016.010openalex-snapshot
A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs
inferredcites →https://doi.org/10.1109/tc.2004.99openalex-snapshot
Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks
inferredcites →https://doi.org/10.1109/tc.2007.70763openalex-snapshot
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems
inferredcites →https://doi.org/10.1109/tvlsi.2016.2572304openalex-snapshot
Timing Analysis of Tasks on Runtime Reconfigurable Processors
inferredcites →https://doi.org/10.1145/1134650.1134665openalex-snapshot
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
inferredcites →https://doi.org/10.1145/1159974.1134665openalex-snapshot
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
inferredcites →https://doi.org/10.1145/1968502.1968509openalex-snapshot
The Instruction-Set Extension Problem
inferredcites →https://doi.org/10.1145/3014059openalex-snapshot
Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors
inferredcites →https://doi.org/10.1145/384196.384230openalex-snapshot
Parametric Timing Analysis

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-16949-7_1openalex-snapshot
i-Core: A Runtime-Reconfigurable Processor Platform for Cyber-Physical Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-42921-7_17openalex-snapshot
On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS$$^{64}$$
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_10openalex-snapshot
Countermeasures Against Voltage Attacks in Multi-tenant FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-031-45410-3_11openalex-snapshot
Application Design Issues
inferred← citeshttps://doi.org/10.1007/978-981-15-6401-7_51-1openalex-snapshot
Dynamic and Partial Reconfiguration of FPGAs
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_51openalex-snapshot
Dynamic and Partial Reconfiguration of FPGAs
inferred← citeshttps://doi.org/10.1007/s11227-019-03056-5openalex-snapshot
A link-elimination partitioning approach for application graph mapping in reconfigurable computing systems
inferred← citeshttps://doi.org/10.1016/j.future.2021.09.037openalex-snapshot
Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey
inferred← citeshttps://doi.org/10.1016/j.matpr.2021.04.229openalex-snapshot
Partial Dynamic reconfiguration and task sceduling framework for FPGA: A survey with concepts, constraints and trends
inferred← citeshttps://doi.org/10.1016/j.parco.2022.102922openalex-snapshot
Spatial- and time- division multiplexing in CNN accelerator
inferred← citeshttps://doi.org/10.1109/access.2019.2943179openalex-snapshot
A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing
inferred← citeshttps://doi.org/10.1109/cstic61820.2024.10531952openalex-snapshot
Preemptive FPGA Scheduling Based on Dynamic Partial Reconfiguration
inferred← citeshttps://doi.org/10.1109/etfa45728.2021.9613666openalex-snapshot
Offloading Accelerator-intensive Workloads in CPU-GPU Heterogeneous Processors
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643485openalex-snapshot
LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs
inferred← citeshttps://doi.org/10.1109/ipdpsw.2019.00027openalex-snapshot
An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1109/ipdpsw52791.2021.00074openalex-snapshot
Time-Division Multiplexing for FPGA Considering CNN Model Switch Time
inferred← citeshttps://doi.org/10.1109/rtas65571.2025.00040openalex-snapshot
MATCH: Real-Time Scheduling of Multiple and Parallel Data Copies in Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1109/rtas65571.2025.00043openalex-snapshot
HARD: Hardening Real-Time Scheduling and Analysis for Accelerator Enabled Computing
inferred← citeshttps://doi.org/10.1109/rtss66672.2025.00039openalex-snapshot
DERCA: DetERministic Cycle-Level Accelerator on Reconfigurable Platforms in DNN-Enabled Real-Time Safety-Critical Systems
inferred← citeshttps://doi.org/10.1109/tc.2025.3573602openalex-snapshot
Real-Time Scheduling and Analysis of Fixed-Priority Tasks on a Basic Heterogeneous Architecture With Multiple CPUs and Many PEs
inferred← citeshttps://doi.org/10.1109/ucet.2019.8881834openalex-snapshot
Position Paper: Prototyping Autonomous Vehicles Applications with Heterogeneous Multi-FpgaSystems
inferred← citeshttps://doi.org/10.1145/3403702openalex-snapshot
Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs
inferred← citeshttps://doi.org/10.1145/3508352.3549409openalex-snapshot
SHAPE
inferred← citeshttps://doi.org/10.1145/3643825openalex-snapshot
Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial Reconfiguration
inferred← citeshttps://doi.org/10.1145/3716368.3735215openalex-snapshot
ART: Customizing Accelerators for DNN-Enabled Real-Time Safety-Critical Systems
inferred← citeshttps://doi.org/10.1145/3797248.3816189openalex-snapshot
To Overlay or to Customize? Revisiting Architectural Choices in Heterogeneous Systems
inferred← citeshttps://doi.org/10.3390/electronics9091362openalex-snapshot
Sw/Hw Partitioning and Scheduling on Region-Based Dynamic Partial Reconfigurable System-on-Chip
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