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A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4614-1225-0openalex-snapshot
Partial Reconfiguration on FPGAs : Architectures, Tools and Applications
inferredcites →https://doi.org/10.1007/978-3-319-16214-0_7openalex-snapshot
Preemptive Hardware Multitasking in ReconOS
inferredcites →https://doi.org/10.1007/978-3-642-19475-7_26openalex-snapshot
FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA
inferredcites →https://doi.org/10.1007/s11241-005-0507-9openalex-snapshot
Measuring the Performance of Schedulability Tests
inferredcites →https://doi.org/10.1007/s11241-007-9012-7openalex-snapshot
Controller Area Network (CAN) schedulability analysis: Refuted, revisited and revised
inferredcites →https://doi.org/10.1016/j.sysarc.2004.06.003openalex-snapshot
An FPGA-based coprocessor for real-time fieldbus traffic scheduling—architecture and implementation
inferredcites →https://doi.org/10.1109/date.2003.1253733openalex-snapshot
Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip
inferredcites →https://doi.org/10.1109/date.2007.364578openalex-snapshot
Hard Real-Time Reconfiguration Port Scheduling
inferredcites →https://doi.org/10.1109/ecrts.2015.15openalex-snapshot
Timing Analysis of Fixed Priority Self-Suspending Sporadic Tasks
inferredcites →https://doi.org/10.1109/fccm.2012.17openalex-snapshot
Go Ahead: A Partial Reconfiguration Framework
inferredcites →https://doi.org/10.1109/fpga.1995.241945openalex-snapshot
HGA: A Hardware-Based Genetic Algorithm
inferredcites →https://doi.org/10.1109/fpl.2009.5272418openalex-snapshot
Cooperative multithreading in dynamically reconfigurable systems
inferredcites →https://doi.org/10.1109/les.2015.2396069openalex-snapshot
Scheduling Dynamic Hard Real-Time Task Sets on Fully and Partially Reconfigurable Platforms
inferredcites →https://doi.org/10.1109/rtas.2007.25openalex-snapshot
Optimizing the FPGA Implementation of HRT Systems
inferredcites →https://doi.org/10.1109/tc.2007.70763openalex-snapshot
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems
inferredcites →https://doi.org/10.1109/wises.2005.1438720openalex-snapshot
Periodic real-time scheduling for FPGA computers
inferredcites →https://doi.org/10.1145/1723112.1723190openalex-snapshot
Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only)
inferredcites →https://doi.org/10.1145/2513683.2513688openalex-snapshot
Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ
inferredcites →https://doi.org/10.1145/2629639openalex-snapshot
Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)
inferredcites →https://doi.org/10.1145/968280.968311openalex-snapshot
An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm
inferredcites →https://doi.org/10.48550/arxiv.1508.07142openalex-snapshot
Transparent hardware synthesis of Java for predictable large-scale distributed systems
inferredcites →https://doi.org/10.5170/cern-2000-010.307openalex-snapshot
Recent progress in field programmable logic
inferredcites →https://doi.org/10.5555/1266366.1266395openalex-snapshot
Hard real-time reconfiguration port scheduling
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Timing isolation and improved scheduling of deep neural networks for real‐time systems
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i-Core: A Runtime-Reconfigurable Processor Platform for Cyber-Physical Systems
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On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS$$^{64}$$
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Application Design Issues
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On the ineffectiveness of 1/m-based interference bounds in the analysis of global EDF and FIFO scheduling
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Many suspensions, many problems: a review of self-suspending tasks in real-time systems
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Supporting AI-powered real-time cyber-physical systems on heterogeneous platforms via hypervisor technology
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A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration
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Using dynamic partial reconfiguration of FPGAs in real-Time systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2022.102416openalex-snapshot
Optimized partitioning and priority assignment of real-time applications on heterogeneous platforms with hardware acceleration
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Reconfigurable architecture of real-time data processing for laser-aided electron density diagnostics on EAST Tokamak
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A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing
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SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms
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High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks
inferred← citeshttps://doi.org/10.1109/access.2026.3731807openalex-snapshot
CertiHybrid-B: A Lyapunov-Budget-Aware Quantized Neural Predictive Controller for Certification-Oriented RTOS–FPGA Co-Architectures
inferred← citeshttps://doi.org/10.1109/ahs.2017.8046375openalex-snapshot
Timing-aware FPGA partitioning for real-time applications under dynamic partial reconfiguration
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NEUROBOX: An Open-Source Suite for the Flow Control of EEG Experiments
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Response-Time Analysis of DAG Tasks Supporting Heterogeneous Computing
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An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems
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A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms
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Timing Analysis of Fixed Priority Self-Suspending Sporadic Tasks
inferred← citeshttps://doi.org/10.1109/etfa45728.2021.9613666openalex-snapshot
Offloading Accelerator-intensive Workloads in CPU-GPU Heterogeneous Processors
inferred← citeshttps://doi.org/10.1109/fccm48280.2020.00026openalex-snapshot
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
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Design for ReConfigurability: An Electronic System Level Methodology to Exploit Reconfigurable Platforms
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An FPGA-based real-time radar coordinate transformation by jointly exploiting MicroBlaze and Programmable Logic
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WCET Guarantees for Opportunistic Runtime Reconfiguration
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A Systematic Methodology for Time-multiplexing Algorithms on a Reconfigurable System-on-Chip
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The AMPERE Project: : A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimization
inferred← citeshttps://doi.org/10.1109/jiot.2018.2863545openalex-snapshot
ChamelIoT: An Agnostic Operating System Framework for Reconfigurable IoT Devices
inferred← citeshttps://doi.org/10.1109/les.2017.2714844openalex-snapshot
CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/les.2019.2953253openalex-snapshot
A Safe, Secure, and Predictable Software Architecture for Deep Learning in Safety-Critical Systems
inferred← citeshttps://doi.org/10.1109/les.2020.3004302openalex-snapshot
Dynamic Partial Reconfiguration Profitability for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/les.2023.3305401openalex-snapshot
Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection
inferred← citeshttps://doi.org/10.1109/meco.2019.8760036openalex-snapshot
Self-adaptive loop for CPSs: is the Dynamic Partial Reconfiguration profitable?
inferred← citeshttps://doi.org/10.1109/norchip.2017.8124984openalex-snapshot
Can real-time systems benefit from dynamic partial reconfiguration?
inferred← citeshttps://doi.org/10.1109/rtas.2018.00026openalex-snapshot
Shared-Resource-Centric Limited Preemptive Scheduling: A Comprehensive Study of Suspension-Based Partitioning Approaches
inferred← citeshttps://doi.org/10.1109/rtas52030.2021.00013openalex-snapshot
Event-Driven Delay-Induced Tasks: Model, Analysis, and Applications
inferred← citeshttps://doi.org/10.1109/rtas58335.2023.00020openalex-snapshot
Scheduling Periodic Segmented Self-Suspending Tasks without Timing Anomalies
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MATCH: Real-Time Scheduling of Multiple and Parallel Data Copies in Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1109/rtas68450.2026.00033openalex-snapshot
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoCs with Multi-Core DPUs
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Schedulability Analysis and Priority Assignment for Segmented Self-Suspending Tasks
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Segment-Level FP-Scheduling in FreeRTOS
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The SRP Resource Sharing Protocol for Self-Suspending Tasks
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Work-In-Progress: Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges
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Requirement-Based Analysis of Self-Suspending Tasks under EDF
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Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs
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Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs
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Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs
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