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A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Random Register Renaming to Foil DPA
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On the Cost of Lazy Engineering for Masked Software Implementations
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Correlation Power Analysis with a Leakage Model
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Private Circuits: Securing Hardware against Probing Attacks
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A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
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Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World
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Power Analysis of Atmel CryptoMemory – Recovering Keys from Secure EEPROMs
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Consolidating Masking Schemes
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DPA, Bitslicing and Masking at 1 GHz
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PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision
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Introduction to differential power analysis
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Univariate side channel attacks and leakage modeling
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Introduction to the Cortex-M Processor Family
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The Designer's Guide to the Cortex-M Processor Family
inferredcites →https://doi.org/10.1016/j.ipl.2014.09.030openalex-snapshot
Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software
inferredcites →https://doi.org/10.1016/j.jss.2013.02.021openalex-snapshot
A fault induction technique based on voltage underfeeding with application to attacks against AES and RSA
inferredcites →https://doi.org/10.1016/j.micpro.2016.01.004openalex-snapshot
Side-channel leakage models for RISC instruction set architectures from empirical data
inferredcites →https://doi.org/10.1049/iet-ifs:20060112openalex-snapshot
Testing power-analysis attack susceptibility in register-transfer level designs
inferredcites →https://doi.org/10.1109/fdtc.2009.44openalex-snapshot
KeeLoq and Side-Channel Analysis-Evolution of an Attack
inferredcites →https://doi.org/10.1109/itcc.2004.1286711openalex-snapshot
Power-analysis attack on an ASIC AES implementation
inferredcites →https://doi.org/10.1109/mse.2009.5270820openalex-snapshot
FreePDK v2.0: Transitioning VLSI education towards nanometer variation-aware designs
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Using Virtual Secure Circuit to Protect Embedded Software from Side-Channel Attacks
inferredcites →https://doi.org/10.1109/tc.2013.219openalex-snapshot
Automatic Application of Power Analysis Countermeasures
inferredcites →https://doi.org/10.1109/tcad.2005.855939openalex-snapshot
A digital design flow for secure integrated circuits
inferredcites →https://doi.org/10.1109/tcad.2015.2430320openalex-snapshot
The MEET Approach: Securing Cryptographic Embedded Software Against Side Channel Attacks
inferredcites →https://doi.org/10.1109/tdsc.2007.70234openalex-snapshot
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips
inferredcites →https://doi.org/10.1145/1015047.1015050openalex-snapshot
Statistics and secret leakage
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Simulation models for side-channel information leaks
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Power-gated MOS current mode logic (PG-MCML)
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On the vulnerability of FPGA bitstream encryption against power analysis attacks
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A code morphing methodology to automate power analysis countermeasures
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Compiler-based side channel vulnerability analysis and optimized countermeasures application
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A Multiple Equivalent Execution Trace Approach to Secure Cryptographic Embedded Software
inferredcites →https://doi.org/10.1145/2768566.2768567openalex-snapshot
Side-channel analysis of MAC-Keccak hardware implementations
inferredcites →https://doi.org/10.1145/2810103.2813626openalex-snapshot
Leakage-Resilient Authentication and Encryption from Symmetric Cryptographic Primitives
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Physical key extraction attacks on PCs
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ECDSA Key Extraction from Mobile Devices via Nonintrusive Physical Side Channels
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Unbiased Estimation of Certain Correlation Coefficients
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Integrating Side Channel Security in the FPGA Hardware Design Flow
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On the Effectiveness of True Random Number Generators Implemented on FPGAs
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Masking Out of Order: Side-Channel Leaks from Software-Masked Cryptography on Out-of-Order Processors and the Impact of Different Clock Frequencies
inferred← citeshttps://doi.org/10.1007/s11227-021-03927-wopenalex-snapshot
Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process
inferred← citeshttps://doi.org/10.1016/j.csi.2021.103569openalex-snapshot
Side-channel information leakage analysis and countermeasures in an embedded CPU microarchitecture
inferred← citeshttps://doi.org/10.1016/j.jisa.2020.102561openalex-snapshot
Side-channel leakage assessment metrics and methodologies at design cycle: A case study for a cryptosystem
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Microarchitectural Side-Channel Threats, Weaknesses and Mitigations: A Systematic Mapping Study
inferred← citeshttps://doi.org/10.1109/asp-dac52403.2022.9712551openalex-snapshot
FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs
inferred← citeshttps://doi.org/10.1109/naecon61878.2024.10670646openalex-snapshot
Power Side-Channel Verification in Hardware Designs
inferred← citeshttps://doi.org/10.1109/recosoc48741.2019.9034935openalex-snapshot
Analysis and countermeasures to side-channel attacks: a hardware design perspective
inferred← citeshttps://doi.org/10.1109/tcad.2019.2926389openalex-snapshot
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks
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Design of Side-Channel-Resistant Power Monitors
inferred← citeshttps://doi.org/10.1117/12.2642112openalex-snapshot
Resistance to side-channel attacks of CPU based on random power consumption disturbance strategy
inferred← citeshttps://doi.org/10.1145/3229631.3239368openalex-snapshot
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems
inferred← citeshttps://doi.org/10.1145/3424978.3425052openalex-snapshot
Countermeasures Against Information Leakage Induced by Data Serialization Effects in a RISC CPU
inferred← citeshttps://doi.org/10.1145/3721294openalex-snapshot
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs
inferred← citeshttps://doi.org/10.1145/3768154openalex-snapshot
Boosting Cryptographic ICs’ Side-Channel Resistance: A Formal Framework for Automatic Identification and Protection of Leaky Paths
inferred← citeshttps://doi.org/10.3390/electronics14051007openalex-snapshot
A Weak-PUF-Assisted Strong PUF with Inherent Security Using Metastability Implemented on FPGAs
inferred← citeshttps://doi.org/10.46586/tches.v2020.i2.73-98openalex-snapshot
FENL: an ISE to mitigate analogue micro-architectural leakage
inferred← citeshttps://doi.org/10.46586/tches.v2022.i1.175-220openalex-snapshot
MIRACLE: MIcRo-ArChitectural Leakage Evaluation
inferred← citeshttps://doi.org/10.70675/107b8fa7z46afz4516z86efz1948ee6b8cb4openalex-snapshot
(On) The Impact of the Micro-architecture on Countermeasures against Side-Channel Attacks
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