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Power-gated MOS current mode logic (PG-MCML)
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/1-4020-5081-xopenalex-snapshot
Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies
inferredcites →https://doi.org/10.1007/11545262_13openalex-snapshot
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_2openalex-snapshot
Correlation Power Analysis with a Leakage Model
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_11openalex-snapshot
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology
inferredcites →https://doi.org/10.1007/978-3-540-74735-2_21openalex-snapshot
Power Analysis Resistant AES Implementation with Instruction Set Extensions
inferredcites →https://doi.org/10.1007/978-3-642-04138-9_15openalex-snapshot
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
inferredcites →https://doi.org/10.1016/s1353-4858(10)70006-4openalex-snapshot
Advanced Encryption Standard (AES)
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/4.910495openalex-snapshot
Dynamic current mode logic (DyCML): a new low-power high-performance logic style
inferredcites →https://doi.org/10.1109/4.924861openalex-snapshot
0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation
inferredcites →https://doi.org/10.1109/esscir.1998openalex-snapshot
Proceedings of the 24th European Solid-State Circuits Conference
inferredcites →https://doi.org/10.1109/iscas.2004.1329007openalex-snapshot
Adaptable MOS current mode logic for use in a multi-band RF prescaler
inferredcites →https://doi.org/10.1109/iscas.2004.1329017openalex-snapshot
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector
inferredcites →https://doi.org/10.1109/iwsoc.2004.1openalex-snapshot
10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 /spl mu/m CMOS
inferredcites →https://doi.org/10.1145/1403375.1403581openalex-snapshot
A generic standard cell design methodology for differential circuit styles
inferredcites →https://doi.org/10.1201/b16944-165openalex-snapshot
of Lecture Notes in Computer Science, pages 200-212.
inferredcites →https://doi.org/10.6028/nbs.fips.79openalex-snapshot
American National Standard magnetic tape labels and file structure for information interchange
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-19185-5_9openalex-snapshot
Hardware Security Primitives Based on Emerging Technologies
inferred← citeshttps://doi.org/10.1007/978-3-319-69453-5_1openalex-snapshot
Physical Attacks and Beyond
inferred← citeshttps://doi.org/10.1007/s10586-018-1917-5openalex-snapshot
Design and development of high performance MOS current mode logic (MCML) processor for fast and power efficient computing
inferred← citeshttps://doi.org/10.1109/acomp.2019.00030openalex-snapshot
Designing of Standard Cell Library for GBONOR Approach
inferred← citeshttps://doi.org/10.1109/atc.2013.6698126openalex-snapshot
Low power optical transceivers for switched interconnect networks
inferred← citeshttps://doi.org/10.1109/iccd.2015.7357161openalex-snapshot
Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime
inferred← citeshttps://doi.org/10.1109/icspc51351.2021.9451682openalex-snapshot
A Survey on Recent Detection Methods of the Hardware Trojans
inferred← citeshttps://doi.org/10.1109/isqed.2014.6783370openalex-snapshot
Sense Amplifier Pass Transistor Logic for energy efficient and DPA-resistant AES circuit
inferred← citeshttps://doi.org/10.1109/isvlsi.2016.93openalex-snapshot
Hardware Security Challenges Beyond CMOS: Attacks and Remedies
inferred← citeshttps://doi.org/10.1109/jiot.2023.3265683openalex-snapshot
Securing AES Designs Against Power Analysis Attacks: A Survey
inferred← citeshttps://doi.org/10.1109/nano.2016.7751544openalex-snapshot
Power-gating schemes for super-threshold FinFET CML circuits
inferred← citeshttps://doi.org/10.1109/tetc.2016.2559159openalex-snapshot
Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2455874openalex-snapshot
Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS
inferred← citeshttps://doi.org/10.1142/s0218126620500978openalex-snapshot
Combinational Counters: A Low Overhead Approach to Address DPA Attacks
inferred← citeshttps://doi.org/10.1145/2744769.2744866openalex-snapshot
Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks
inferred← citeshttps://doi.org/10.1145/2800986.2801016openalex-snapshot
MCML Gate Design for Standard Cell Library
inferred← citeshttps://doi.org/10.1145/2902961.2903041openalex-snapshot
Enhancing Hardware Security with Emerging Transistor Technologies
inferred← citeshttps://doi.org/10.1145/3212719openalex-snapshot
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture
inferred← citeshttps://doi.org/10.1145/3386263.3407592openalex-snapshot
Side Channel Attacks vs Approximate Computing
inferred← citeshttps://doi.org/10.1155/2013/217674openalex-snapshot
MCML D-Latch Using Triple-Tail Cells: Analysis and Design
inferred← citeshttps://doi.org/10.2174/1874129001408010286openalex-snapshot
Modeling and Sizing of Power-Gating Single-Rail MOS Current Mode Logic
inferred← citeshttps://doi.org/10.2174/1874129001408010306openalex-snapshot
A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors
inferred← citeshttps://doi.org/10.2174/1874444301406010328openalex-snapshot
Power-Gating Single-Rail MOS Current-Mode Logic Circuits Using High- Threshold PMOS Transistors as Linear Resistors
inferred← citeshttps://doi.org/10.2991/iccsee.2013.424openalex-snapshot
Low-Power Near-threshold MOS Current Mode Logic with Power-Gating Techniques
inferred← citeshttps://doi.org/10.3390/app12052390openalex-snapshot
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
inferred← citeshttps://doi.org/10.3390/electronics4040763openalex-snapshot
Introduction to Hardware Security
inferred← citeshttps://doi.org/10.3850/9783981537079_0992openalex-snapshot
Leverage Emerging Technologies For DPA-Resilient Block Cipher Design
inferred← citeshttps://doi.org/10.3850/9783981537079_0993openalex-snapshot
Using Emerging Technologies for Hardware Security Beyond PUFs
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