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What Your DRAM Power Models Are Not Telling You
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-981-13-0599-3_9openalex-snapshot
Reliability Issues in Flash-Memory-Based Solid-State Drives: Experimental Analysis, Mitigation, Recovery
inferredcites →https://doi.org/10.1109/4.5931openalex-snapshot
A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture
inferredcites →https://doi.org/10.1109/92.365453openalex-snapshot
Bus-invert coding for low-power I/O
inferredcites →https://doi.org/10.1109/dsd.2011.17openalex-snapshot
Improved Power Modeling of DDR SDRAMs
inferredcites →https://doi.org/10.1109/dsn.2015.49openalex-snapshot
Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery
inferredcites →https://doi.org/10.1109/dsn.2015.57openalex-snapshot
Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field
inferredcites →https://doi.org/10.1109/dsn.2015.58openalex-snapshot
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems
inferredcites →https://doi.org/10.1109/dsn.2016.30openalex-snapshot
PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM
inferredcites →https://doi.org/10.1109/hipc.2009.5433222openalex-snapshot
Non-uniform power access in large caches with low-swing wires
inferredcites →https://doi.org/10.1109/hpca.2006.1598122openalex-snapshot
Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM
inferredcites →https://doi.org/10.1109/hpca.2008.4658649openalex-snapshot
Power-Efficient DRAM Speculation
inferredcites →https://doi.org/10.1109/hpca.2010.5416646openalex-snapshot
Delay-Hiding energy management mechanisms for DRAM
inferredcites →https://doi.org/10.1109/hpca.2013.6522354openalex-snapshot
Tiered-latency DRAM: A low latency and low cost DRAM architecture
inferredcites →https://doi.org/10.1109/hpca.2014.6835946openalex-snapshot
Improving DRAM performance by parallelizing refreshes with accesses
inferredcites →https://doi.org/10.1109/hpca.2014.6835956openalex-snapshot
NUAT: A non-uniform access time memory controller
inferredcites →https://doi.org/10.1109/hpca.2014.6835958openalex-snapshot
BigDataBench: A big data benchmark suite from internet services
inferredcites →https://doi.org/10.1109/hpca.2014.6835978openalex-snapshot
Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules
inferredcites →https://doi.org/10.1109/hpca.2015.7056021openalex-snapshot
Exploiting compressed block size as an indicator of future reuse
inferredcites →https://doi.org/10.1109/hpca.2015.7056057openalex-snapshot
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
inferredcites →https://doi.org/10.1109/hpca.2015.7056062openalex-snapshot
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery
inferredcites →https://doi.org/10.1109/hpca.2016.7446064openalex-snapshot
A case for toggle-aware compression for GPU systems
inferredcites →https://doi.org/10.1109/hpca.2016.7446095openalex-snapshot
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
inferredcites →https://doi.org/10.1109/hpca.2016.7446096openalex-snapshot
ChargeCache: Reducing DRAM latency by exploiting row access locality
inferredcites →https://doi.org/10.1109/hpca.2017.58openalex-snapshot
Architecting an Energy-Efficient DRAM System for GPUs
inferredcites →https://doi.org/10.1109/hpca.2017.61openalex-snapshot
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques
inferredcites →https://doi.org/10.1109/hpca.2017.62openalex-snapshot
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
inferredcites →https://doi.org/10.1109/hpca.2018.00026openalex-snapshot
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices
inferredcites →https://doi.org/10.1109/hpca.2018.00050openalex-snapshot
HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness
inferredcites →https://doi.org/10.1109/iccd.2006.4380850openalex-snapshot
Improving Power and Data Efficiency with Threaded Memory Modules
inferredcites →https://doi.org/10.1109/iccd.2012.6378619openalex-snapshot
SECRET: Selective error correction for refresh energy reduction in DRAMs
inferredcites →https://doi.org/10.1109/iccd.2012.6378623openalex-snapshot
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime
inferredcites →https://doi.org/10.1109/iccd.2013.6657034openalex-snapshot
Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation
inferredcites →https://doi.org/10.1109/iedm.1996.553853openalex-snapshot
Trench storage node technology for gigabit DRAM generations
inferredcites →https://doi.org/10.1109/iedm.2010.5703348openalex-snapshot
Memory technology trend and future challenges
inferredcites →https://doi.org/10.1109/imw.2013.6582088openalex-snapshot
Memory scaling: A systems architecture perspective
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/isqed.2006.43openalex-snapshot
Data Replication in Banked DRAMs for Reducing Energy Consumption
inferredcites →https://doi.org/10.1109/jproc.2017.2713127openalex-snapshot
Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives
inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
inferredcites →https://doi.org/10.1109/lca.2015.2414456openalex-snapshot
Ramulator: A Fast and Extensible DRAM Simulator
inferredcites →https://doi.org/10.1109/mc.2003.1250880openalex-snapshot
Energy management for commercial servers
inferredcites →https://doi.org/10.1109/mdat.2017.2705144openalex-snapshot
A Platform to Analyze DDR3 DRAM’s Power and Retention Time
inferredcites →https://doi.org/10.1109/micro.2008.4771792openalex-snapshot
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
inferredcites →https://doi.org/10.1109/micro.2010.42openalex-snapshot
Understanding the Energy Consumption of Dynamic Random Access Memories
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/micro.2012.21openalex-snapshot
Rethinking DRAM Power Modes for Energy Proportionality
inferredcites →https://doi.org/10.1109/mm.2010.102openalex-snapshot
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue
inferredcites →https://doi.org/10.1109/mm.2010.43openalex-snapshot
Fine-Grained Activation for Power Reduction in DRAM
inferredcites →https://doi.org/10.1109/mm.2012.21openalex-snapshot
Active Low-Power Modes for Main Memory with MemScale
inferredcites →https://doi.org/10.1109/pact.2015.51openalex-snapshot
Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM
inferredcites →https://doi.org/10.1109/tcad.2012.2185930openalex-snapshot
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
inferredcites →https://doi.org/10.1109/tcsii.2009.2015395openalex-snapshot
Data Bus Inversion in High-Speed Memory Applications
inferredcites →https://doi.org/10.1109/tvlsi.2009.2020989openalex-snapshot
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
inferredcites →https://doi.org/10.1145/1023833.1023838openalex-snapshot
Dynamic on-chip memory management for chip multiprocessors
inferredcites →https://doi.org/10.1145/1028176.1006719openalex-snapshot
Adaptive Cache Compression for High-Performance Processors
inferredcites →https://doi.org/10.1145/1080695.1069978openalex-snapshot
A Robust Main-Memory Compression Scheme
inferredcites →https://doi.org/10.1145/1273440.1250699openalex-snapshot
Limiting the power consumption of main memory
inferredcites →https://doi.org/10.1145/1542275.1542288openalex-snapshot
Zero-content augmented caches
inferredcites →https://doi.org/10.1145/1669112.1669155openalex-snapshot
Improving memory bank-level parallelism in the presence of prefetching
inferredcites →https://doi.org/10.1145/1815961.1815983openalex-snapshot
Rethinking DRAM design and organization for energy-constrained multi-cores
inferredcites →https://doi.org/10.1145/1840845.1840930openalex-snapshot
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
inferredcites →https://doi.org/10.1145/1998582.1998590openalex-snapshot
Memory power management via dynamic voltage/frequency scaling
inferredcites →https://doi.org/10.1145/2024723.2000100openalex-snapshot
Adaptive granularity memory systems
inferredcites →https://doi.org/10.1145/2248487.2150989openalex-snapshot
Cosmic rays don't strike twice
inferredcites →https://doi.org/10.1145/2366231.2337164openalex-snapshot
Towards energy-proportional datacenter memory with mobile DRAM
inferredcites →https://doi.org/10.1145/2366231.2337202openalex-snapshot
A case for exploiting subarray-level parallelism (SALP) in DRAM
inferredcites →https://doi.org/10.1145/2370816.2370870openalex-snapshot
Base-delta-immediate compression
inferredcites →https://doi.org/10.1145/2508148.2485927openalex-snapshot
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
inferredcites →https://doi.org/10.1145/2508148.2485928openalex-snapshot
An experimental study of data retention behavior in modern DRAM devices
inferredcites →https://doi.org/10.1145/2637364.2591994openalex-snapshot
Neighbor-cell assisted error correction for MLC NAND flash memories
inferredcites →https://doi.org/10.1145/2637364.2592000openalex-snapshot
The efficacy of error mitigation techniques for DRAM retention failures
inferredcites →https://doi.org/10.1145/2678373.2665726openalex-snapshot
Flipping bits in memory without accessing them
inferredcites →https://doi.org/10.1145/2749469.2750399openalex-snapshot
A case for core-assisted bottleneck acceleration in GPUs
inferredcites →https://doi.org/10.1145/2775054.2694348openalex-snapshot
Memory Errors in Modern Systems
inferredcites →https://doi.org/10.1145/280756.280792openalex-snapshot
Optimizing the DRAM refresh count for merged DRAM/logic LSIs
inferredcites →https://doi.org/10.1145/2896377.2901453openalex-snapshot
Understanding Latency Variation in Modern DRAM Chips
inferredcites →https://doi.org/10.1145/3023973.3023978openalex-snapshot
A Bank-Wise DRAM Power Model for System Simulations
inferredcites →https://doi.org/10.1145/3078505.3078533openalex-snapshot
Design-Induced Latency Variation in Modern DRAM Chips
inferredcites →https://doi.org/10.1145/3078505.3078590openalex-snapshot
Understanding Reduced-Voltage Operation in Modern DRAM Devices
inferredcites →https://doi.org/10.1145/3123939.3123945openalex-snapshot
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content
inferredcites →https://doi.org/10.1145/3219617.3219659openalex-snapshot
Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
inferredcites →https://doi.org/10.1145/360128.360154openalex-snapshot
Frequent value compression in data caches
inferredcites →https://doi.org/10.1145/383082.383118openalex-snapshot
Memory controller policies for DRAM power management
inferredcites →https://doi.org/10.1145/513918.513973openalex-snapshot
Automatic data migration for reducing energy consumption in multi-bank memory systems
inferredcites →https://doi.org/10.1145/996566.996596openalex-snapshot
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
inferredcites →https://doi.org/10.5555/603095.603136openalex-snapshot
Improving memory energy using access pattern classification
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-52794-5_5openalex-snapshot
3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs
inferred← citeshttps://doi.org/10.1007/978-3-030-60939-9_8openalex-snapshot
DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator
inferred← citeshttps://doi.org/10.1007/978-3-031-19568-6_6openalex-snapshot
An Off-Chip Memory Access Optimization for Embedded Deep Learning Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-96473-2_28openalex-snapshot
Migration and Replacement in Main Memory and Cache in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1007/978-981-96-8383-3_1openalex-snapshot
Introduction: What Is ‘Slow Electronics.’
inferred← citeshttps://doi.org/10.1007/s10766-022-00727-4openalex-snapshot
DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses
inferred← citeshttps://doi.org/10.1016/j.future.2026.108486openalex-snapshot
BinDRAM: Binary neural network on unmodified commodity DRAM
inferred← citeshttps://doi.org/10.1016/j.microrel.2024.115467openalex-snapshot
Revisiting row hammer: A deep dive into understanding and resolving the issue
inferred← citeshttps://doi.org/10.1016/j.simpat.2024.103032openalex-snapshot
Survey of CPU and memory simulators in computer architecture: A comprehensive analysis including compiler integration and emerging technology applications
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103310openalex-snapshot
PARL: Page Allocation in hybrid main memory using Reinforcement Learning
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103710openalex-snapshot
CADM: Content addressable commodity off-the-shelf DRAM-based genome classifier
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103942openalex-snapshot
CommoDIMM: Matrix computations for AI applications on commodity unmodified DRAM
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.104053openalex-snapshot
Row-Buffer-Stable Scheduling of DNN for DRAM-PIM via Hardware-Derived Admissibility Bounds
inferred← citeshttps://doi.org/10.1038/s44335-024-00004-2openalex-snapshot
PIM GPT a hybrid process in memory accelerator for autoregressive transformers
inferred← citeshttps://doi.org/10.1103/1sgm-dhysopenalex-snapshot
Thermodynamic Constraints in Dynamic Random-Access Memory Cells: Experimental Verification of Energy Efficiency Limits in Information Erasure
inferred← citeshttps://doi.org/10.1109/access.2021.3061349openalex-snapshot
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process
inferred← citeshttps://doi.org/10.1109/access.2021.3088893openalex-snapshot
ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM
inferred← citeshttps://doi.org/10.1109/access.2024.3514377openalex-snapshot
Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems
inferred← citeshttps://doi.org/10.1109/aicas59952.2024.10595947openalex-snapshot
A Low-power 3D Point Clouds Matching Processor with 1D-CNN Prediction and CAM-based In-memory kNN Searching
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00073openalex-snapshot
POMMEL: Exploring Off-Chip Memory Energy & Power Consumption in Convolutional Neural Network Accelerators
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408512openalex-snapshot
SAGe: A Lightweight Algorithm-Architecture Co-Design for Mitigating the Data Preparation Bottleneck in Large-Scale Genome Sequence Analysis
inferred← citeshttps://doi.org/10.1109/icde60146.2024.00300openalex-snapshot
Accelerating Aggregation Using a Real Processing-in-Memory System
inferred← citeshttps://doi.org/10.1109/icin60470.2024.10494488openalex-snapshot
Memory Bandwidth Throttling to Maximise Performance and Reduce Power Consumption
inferred← citeshttps://doi.org/10.1109/ipdpsw63119.2024.00073openalex-snapshot
A Comparative Study on Simulation Frameworks for AI Accelerator Evaluation
inferred← citeshttps://doi.org/10.1109/ispass61541.2024.00015openalex-snapshot
MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems
inferred← citeshttps://doi.org/10.1109/lca.2023.3341830openalex-snapshot
DRAMA: Commodity DRAM Based Content Addressable Memory
inferred← citeshttps://doi.org/10.1109/lca.2024.3384259openalex-snapshot
MajorK: Majority Based k mer Matching in Commodity DRAM
inferred← citeshttps://doi.org/10.1109/lca.2025.3615711openalex-snapshot
Calibrating DRAMPower Model for HPC: A Runtime Perspective From Real-Time Measurements
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00074openalex-snapshot
Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations
inferred← citeshttps://doi.org/10.1109/tc.2025.3644342openalex-snapshot
SCRec: A Scalable Computational Storage System With Statistical Sharding and Tensor-Train Decomposition for Recommendation Models
inferred← citeshttps://doi.org/10.1109/tcsi.2021.3081623openalex-snapshot
Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications
inferred← citeshttps://doi.org/10.1109/tcsi.2024.3523525openalex-snapshot
C 2 IM-NN: A Low-Power 3D Point Clouds Matching Processor With 1D-CNN Prediction and CAM-Based In-Memory k-NN Searching
inferred← citeshttps://doi.org/10.1109/tcsii.2022.3150030openalex-snapshot
Optimizing Off-Chip Memory Access for Deep Neural Network Accelerator
inferred← citeshttps://doi.org/10.1109/ted.2025.3628603openalex-snapshot
A Scalable Cylindrical Ferroelectric Tunnel Junction Architecture Enabling a New Class Memory for AI Applications
inferred← citeshttps://doi.org/10.1109/vlsid64188.2025.00102openalex-snapshot
Efficient Mitigation of DRAM Row Buffer Conflict Using Request Clustering in Manycore Systems
inferred← citeshttps://doi.org/10.1145/3352020.3352024openalex-snapshot
Analysis of DAWNBench, a Time-to-Accuracy Machine Learning Performance Benchmark
inferred← citeshttps://doi.org/10.1145/3419468openalex-snapshot
Leakage-Aware Dynamic Thermal Management of 3D Memories
inferred← citeshttps://doi.org/10.1145/3476999openalex-snapshot
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks
inferred← citeshttps://doi.org/10.1145/3565053.3565057openalex-snapshot
Using Many Small 1T1C Memory Arrays in a Large and Dense Multicore Processor
inferred← citeshttps://doi.org/10.1145/3579371.3589051openalex-snapshot
DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory
inferred← citeshttps://doi.org/10.1145/3689031.3717498openalex-snapshot
CRAVE: Analyzing Cross-Resource Interaction to Improve Energy Efficiency in Systems-on-Chip
inferred← citeshttps://doi.org/10.1145/3716368.3735168openalex-snapshot
BrIM: A Branching In-Memory Accelerator
inferred← citeshttps://doi.org/10.1145/3718390openalex-snapshot
FairyWREN: A Sustainable Cache for Emerging Write-Read-Erase Flash Interfaces
inferred← citeshttps://doi.org/10.1145/3721848.3721850openalex-snapshot
DRAMPower 5: An Open-Source Power Simulator for Current Generation DRAM Standards
inferred← citeshttps://doi.org/10.1145/3723851.3723857openalex-snapshot
Where are the Joules? Energy Demand Analysis of Heterogeneous Memory Technologies
inferred← citeshttps://doi.org/10.1145/3844618openalex-snapshot
Cambricon-FlexLLM: A Flexible Chiplet-Based Hybrid Architecture for On-Device 70B LLM Inference
inferred← citeshttps://doi.org/10.1147/jrd.2019.2934048openalex-snapshot
Processing-in-memory: A workload-driven perspective
inferred← citeshttps://doi.org/10.1364/psc.2020.psw1f.5openalex-snapshot
Photonic Memory Disaggregation in Datacenters
inferred← citeshttps://doi.org/10.14778/3579075.3579077openalex-snapshot
PetPS: Supporting Huge Embedding Models with Persistent Memory
inferred← citeshttps://doi.org/10.3390/en17092225openalex-snapshot
Investigation of Energy and Power Characteristics of Various Matrix Multiplication Algorithms
inferred← citeshttps://doi.org/10.3390/jlpea12020029openalex-snapshot
Low-Overhead Reinforcement Learning-Based Power Management Using 2QoSM
inferred← citeshttps://doi.org/10.3390/s23042223openalex-snapshot
Lightweight and Energy-Aware Monocular Depth Estimation Models for IoT Embedded Devices: Challenges and Performances in Terrestrial and Underwater Scenarios
inferred← citeshttps://doi.org/10.5772/intechopen.111926openalex-snapshot
End-to-End Benchmarking of Chiplet-Based In-Memory Computing
inferred← citeshttps://doi.org/10.70675/28b94703z5e9cz4e95z9f32z0b2d97de57ffopenalex-snapshot
Exploration and conception of computing architectures of type computing in-memory based on emerging non volatile memories
inferred← citeshttps://doi.org/10.7717/peerj-cs.359openalex-snapshot
Addressing multiple bit/symbol errors in DRAM subsystem
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