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Writeback-Aware LLC Management for PCM-Based Main Memory Systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s11390-015-1509-2openalex-snapshot
A Survey of Phase Change Memory Systems
inferredcites →https://doi.org/10.1109/dac.2018.8465880openalex-snapshot
Thermal-aware Optimizations of ReRAM-based Neuromorphic Computing Systems
inferredcites →https://doi.org/10.1109/hpca.2010.5416645openalex-snapshot
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing
inferredcites →https://doi.org/10.1109/hpca.2014.6835933openalex-snapshot
Adaptive placement and migration policy for an STT-RAM-based hybrid cache
inferredcites →https://doi.org/10.1109/hpca.2015.7056056openalex-snapshot
Overcoming the challenges of crossbar resistive memory architectures
inferredcites →https://doi.org/10.1109/hpca.2017.45openalex-snapshot
Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor
inferredcites →https://doi.org/10.1109/iccd.2014.6974684openalex-snapshot
Loose-Ordering Consistency for persistent memory
inferredcites →https://doi.org/10.1109/ipdps.2016.58openalex-snapshot
Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System
inferredcites →https://doi.org/10.1109/isca.2008.37openalex-snapshot
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
inferredcites →https://doi.org/10.1109/isca.2016.52openalex-snapshot
Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs
inferredcites →https://doi.org/10.1109/isca.2016.66openalex-snapshot
Boosting Access Parallelism to PCM-Based Main Memory
inferredcites →https://doi.org/10.1109/ispass.2013.6557176openalex-snapshot
Evaluating STT-RAM as an energy-efficient main memory alternative
inferredcites →https://doi.org/10.1109/isscc.2012.6176872openalex-snapshot
A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth
inferredcites →https://doi.org/10.1109/lca.2015.2402435openalex-snapshot
NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems
inferredcites →https://doi.org/10.1109/tc.2013.76openalex-snapshot
Throughput Enhancement for Phase Change Memories
inferredcites →https://doi.org/10.1109/tcad.2012.2185930openalex-snapshot
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
inferredcites →https://doi.org/10.1145/1394608.1382148openalex-snapshot
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555761openalex-snapshot
Hybrid cache architecture with disparate memory technologies
inferredcites →https://doi.org/10.1145/1629575.1629589openalex-snapshot
Better I/O through byte-addressable, persistent memory
inferredcites →https://doi.org/10.1145/1669112.1669178openalex-snapshot
Adaptive line placement with the set balancing cache
inferredcites →https://doi.org/10.1145/2830772.2830805openalex-snapshot
Efficient persist barriers for multicores
inferredcites →https://doi.org/10.1145/2897937.2898110openalex-snapshot
Write-back aware shared last-level cache management for hybrid main memory
inferredcites →https://doi.org/10.1145/3007787.3001211openalex-snapshot
Boosting access parallelism to PCM-based main memory
inferredcites →https://doi.org/10.1145/360128.360132openalex-snapshot
Eager writeback - a technique for improving bandwidth utilization
inferredcites →https://doi.org/10.1147/rd.524.0465openalex-snapshot
Phase-change random access memory: A scalable technology
inferredcites →https://doi.org/10.23919/date.2017.7927151openalex-snapshot
MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems
inferredcites →https://doi.org/10.23919/date.2018.8342051openalex-snapshot
WALL: A writeback-aware LLC management for PCM-based main memory systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-87059-1_11openalex-snapshot
Nonvolatile Memory-Based Internet of Things: A Survey
inferred← citeshttps://doi.org/10.1007/s10586-025-05130-5openalex-snapshot
An efficient low aggressiveness portion (ELAP) cache replacement policy for systems with non-volatile main memory
inferred← citeshttps://doi.org/10.1007/s10619-022-07421-xopenalex-snapshot
Challenges and future directions for energy, latency, and lifetime improvements in NVMs
inferred← citeshttps://doi.org/10.1016/j.micpro.2022.104462openalex-snapshot
An Architectural-Level Reliability Improvement Scheme in STT-MRAM Main Memory
inferred← citeshttps://doi.org/10.1109/hpcc-smartcity-dss50907.2020.00024openalex-snapshot
CLOCK-RWRF: A Read-Write-Relative-Frequency Page Replacement Algorithm for PCM and DRAM of Hybrid Memory
inferred← citeshttps://doi.org/10.1109/idciot59759.2024.10467564openalex-snapshot
A Novel Hybrid Memory System based on Non-Volatile Memory for Edge Intelligent IoT Devices
inferred← citeshttps://doi.org/10.1109/tcad.2021.3126680openalex-snapshot
Planting Fast-Growing Forest by Leveraging the Asymmetric Read/Write Latency of NVRAM-Based Systems
inferred← citeshttps://doi.org/10.1145/3358180openalex-snapshot
Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories
inferred← citeshttps://doi.org/10.1145/3381898.3397215openalex-snapshot
Exploiting inter- and intra-memory asymmetries for data mapping in hybrid tiered-memories
inferred← citeshttps://doi.org/10.1145/3687308openalex-snapshot
High Performance and Predictable Shared Last-level Cache for Safety-Critical Systems
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