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Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/16.678551openalex-snapshot
On the retention time distribution of dynamic random access memory (DRAM)
inferredcites →https://doi.org/10.1109/hpca.2013.6522314openalex-snapshot
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
inferredcites →https://doi.org/10.1109/hpca.2013.6522336openalex-snapshot
Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies
inferredcites →https://doi.org/10.1109/hpca.2013.6522338openalex-snapshot
Disintegrated control for energy-efficient and heterogeneous memory systems
inferredcites →https://doi.org/10.1109/iccd.2011.6081427openalex-snapshot
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems
inferredcites →https://doi.org/10.1109/iccd.2012.6378661openalex-snapshot
Row buffer locality aware caching policies for hybrid memories
inferredcites →https://doi.org/10.1109/isca.2008.37openalex-snapshot
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
inferredcites →https://doi.org/10.1109/isca.2012.6237001openalex-snapshot
RAIDR: Retention-aware intelligent DRAM refresh
inferredcites →https://doi.org/10.1109/iscas.2007.378515openalex-snapshot
Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh
inferredcites →https://doi.org/10.1109/ispass.2013.6557176openalex-snapshot
Evaluating STT-RAM as an energy-efficient main memory alternative
inferredcites →https://doi.org/10.1109/isscc.2012.6176872openalex-snapshot
A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth
inferredcites →https://doi.org/10.1109/l-ca.2012.2openalex-snapshot
Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management
inferredcites →https://doi.org/10.1109/led.2009.2023248openalex-snapshot
A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs
inferredcites →https://doi.org/10.1109/mascots.2011.68openalex-snapshot
Characterizing Memory Write References for Efficient Management of Hybrid PCM and DRAM Memory
inferredcites →https://doi.org/10.1109/micro.2007.13openalex-snapshot
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
inferredcites →https://doi.org/10.1109/micro.2007.38openalex-snapshot
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
inferredcites →https://doi.org/10.1109/mm.2010.24openalex-snapshot
Phase-Change Technology and the Future of Main Memory
inferredcites →https://doi.org/10.1109/pact.2009.30openalex-snapshot
Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures
inferredcites →https://doi.org/10.1109/tcad.2012.2185930openalex-snapshot
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
inferredcites →https://doi.org/10.1145/1394608.1382148openalex-snapshot
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1815961.1815983openalex-snapshot
Rethinking DRAM design and organization for energy-constrained multi-cores
inferredcites →https://doi.org/10.1145/1995896.1995911openalex-snapshot
Page placement in hybrid memory systems
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/2579669openalex-snapshot
Refresh pausing in DRAM memory systems
inferredcites →https://doi.org/10.1145/2749469.2750383openalex-snapshot
A fully associative, tagless DRAM cache
inferredcites →https://doi.org/10.1147/rd.462.0187openalex-snapshot
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
inferredcites →https://doi.org/10.1147/rd.524.0465openalex-snapshot
Phase-change random access memory: A scalable technology
inferredcites →https://doi.org/10.1177/109434209100500306openalex-snapshot
The NAS Parallel Benchmarks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11390-020-0780-zopenalex-snapshot
A Survey of Non-Volatile Main Memory Technologies: State-of-the-Arts, Practices, and Future Directions
inferred← citeshttps://doi.org/10.1080/02564602.2022.2127945openalex-snapshot
Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/hpcc-smartcity-dss50907.2020.00024openalex-snapshot
CLOCK-RWRF: A Read-Write-Relative-Frequency Page Replacement Algorithm for PCM and DRAM of Hybrid Memory
inferred← citeshttps://doi.org/10.1109/hpcc/smartcity/dss.2019.00066openalex-snapshot
Access-Aware Self-Adaptive Data Mapping onto 3D-Stacked Hybrid DRAM-PCM Based Chip-Multiprocessor
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753299openalex-snapshot
TESLA: Using microfluidics to thermally stabilize 3D stacked STT-RAM caches
inferred← citeshttps://doi.org/10.1109/ipdps.2018.00076openalex-snapshot
THOR: THermal-aware Optimizations for extending ReRAM Lifetime
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00089openalex-snapshot
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
inferred← citeshttps://doi.org/10.1109/led.2022.3218862openalex-snapshot
HfZrOx Hybrid DRAM/FRAM Arrays Featuring Excellent Endurance and Low Latency
inferred← citeshttps://doi.org/10.1109/sci68648.2025.11333870openalex-snapshot
HyFRAME: A Hybrid Memory Framework for HPC Workloads
inferred← citeshttps://doi.org/10.1109/tc.2019.2906597openalex-snapshot
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories
inferred← citeshttps://doi.org/10.1109/tcad.2018.2819080openalex-snapshot
NVQuery: Efficient Query Processing in Nonvolatile Memory
inferred← citeshttps://doi.org/10.1109/tetc.2016.2642057openalex-snapshot
Resistive CAM Acceleration for Tunable Approximate Computing
inferred← citeshttps://doi.org/10.1145/3149393.3149394openalex-snapshot
Architecting HBM as a high bandwidth, high capacity, self-managed last-level cache
inferred← citeshttps://doi.org/10.1145/3292009openalex-snapshot
Writeback-Aware LLC Management for PCM-Based Main Memory Systems
inferred← citeshttps://doi.org/10.1145/3639038openalex-snapshot
H3DM: A High-bandwidth High-capacity Hybrid 3D Memory Design for GPUs
inferred← citeshttps://doi.org/10.16984/saufenbilder.334645openalex-snapshot
A Survey of Hybrid Main Memory Architectures
inferred← citeshttps://doi.org/10.23919/date.2018.8342051openalex-snapshot
WALL: A writeback-aware LLC management for PCM-based main memory systems
inferred← citeshttps://doi.org/10.3929/ethz-b-000463029openalex-snapshot
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators
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