On the public citation graph

DCMI

https://doi.org/10.1145/3352813
0 signed · 49 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1023/a:1015460304860openalex-snapshot
Achieving Scalable Locality with Time Skewing
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942108openalex-snapshot
Proceedings of the 2019 International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/isca.2014.6853195openalex-snapshot
A reconfigurable fabric for accelerating large-scale datacenter services
inferredcites →https://doi.org/10.1109/ispan.1994.367191openalex-snapshot
Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)
inferredcites →https://doi.org/10.1109/ispdc.2012.17openalex-snapshot
Tuning a Finite Difference Computation for Parallel Vector Processors
inferredcites →https://doi.org/10.1109/lawp.2003.812245openalex-snapshot
Hardware implementation of a three-dimensional finite-difference time-domain algorithm
inferredcites →https://doi.org/10.1109/mm.2006.73openalex-snapshot
IPC Considered Harmful for Multiprocessor Workloads
inferredcites →https://doi.org/10.1109/reconfig44976.2018openalex-snapshot
2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
inferredcites →https://doi.org/10.1109/sbac-pad.2016.18openalex-snapshot
Speeding Up Stencil Computations with Kernel Convolution
inferredcites →https://doi.org/10.1109/sc.2008.5222004openalex-snapshot
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures
inferredcites →https://doi.org/10.1109/tcad.2006.884574openalex-snapshot
Measuring the Gap Between FPGAs and ASICs
inferredcites →https://doi.org/10.1109/tcad.2016.2545408openalex-snapshot
Efficient Hardware Design of Iterative Stencil Loops
inferredcites →https://doi.org/10.1109/tpds.2013.51openalex-snapshot
Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory Bandwidth
inferredcites →https://doi.org/10.1109/tpds.2016.2614981openalex-snapshot
OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology
inferredcites →https://doi.org/10.1109/tsp.2007.898785openalex-snapshot
Design Methodology for Real-Time FPGA-Based Sound Synthesis
inferredcites →https://doi.org/10.1145/1034774.1034777openalex-snapshot
Automatic tiling of iterative stencil loops
inferredcites →https://doi.org/10.1145/125826.126004openalex-snapshot
Seismic modeling at 14 gigaflops on the connection machine
inferredcites →https://doi.org/10.1145/1542275.1542313openalex-snapshot
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
inferredcites →https://doi.org/10.1145/1815961.1815968openalex-snapshot
Understanding sources of inefficiency in general-purpose chips
inferredcites →https://doi.org/10.1145/1941487.1941507openalex-snapshot
The future of microprocessors
inferredcites →https://doi.org/10.1145/2082156.2082168openalex-snapshot
Domain-specific programmable design of scalable streaming-array for power-efficient stencil computation
inferredcites →https://doi.org/10.1145/2463209.2488797openalex-snapshot
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices
inferredcites →https://doi.org/10.1145/2584665openalex-snapshot
Delite
inferredcites →https://doi.org/10.1145/2800788openalex-snapshot
Memory Interface Design for 3D Stencil Kernels on a Massively Parallel Memory System
inferredcites →https://doi.org/10.1145/2842615openalex-snapshot
On How to Accelerate Iterative Stencil Loops
inferredcites →https://doi.org/10.1145/2851497openalex-snapshot
Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices
inferredcites →https://doi.org/10.1145/2927964.2927967openalex-snapshot
Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization
inferredcites →https://doi.org/10.1145/3037697.3037749openalex-snapshot
Moonwalk
inferredcites →https://doi.org/10.1145/3150211openalex-snapshot
Halide
inferredcites →https://doi.org/10.1145/3174243.3174248openalex-snapshot
Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL
inferredcites →https://doi.org/10.1145/3174243.3174251openalex-snapshot
Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing Kernels
inferredcites →https://doi.org/10.1145/3240765.3240850openalex-snapshot
SODA
inferredcites →https://doi.org/10.1145/335231.335246openalex-snapshot
Optimized unrolling of nested loops
inferredcites →https://doi.org/10.1145/357401.357403openalex-snapshot
Decoupled access/execute computer architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-53532-2_1openalex-snapshot
Challenges in the Realm of Embedded Real-Time Image Processing
inferred← citeshttps://doi.org/10.1007/978-3-030-53532-2_2openalex-snapshot
TRP: A Foundational Platform for High-Performance Low-Power Embedded Image Processing
inferred← citeshttps://doi.org/10.1007/978-3-030-53532-2_5openalex-snapshot
STHEM: Productive Implementation of High-Performance Embedded Image Processing Applications
inferred← citeshttps://doi.org/10.1007/s13369-025-10919-yopenalex-snapshot
Exploring Efficient FPGA Acceleration of High-Order 3D Iterative Stencil Loops on Large Data Grids
inferred← citeshttps://doi.org/10.1016/j.future.2022.10.030openalex-snapshot
Near-optimal multi-accelerator architectures for predictive maintenance at the edge
inferred← citeshttps://doi.org/10.1016/j.future.2023.04.019openalex-snapshot
TurboStencil: You only compute once for stencil computation
inferred← citeshttps://doi.org/10.1109/access.2023.3252002openalex-snapshot
Casper: Accelerating Stencil Computations Using Near-Cache Processing
inferred← citeshttps://doi.org/10.1109/asap57973.2023.00025openalex-snapshot
FAWS: FPGA Acceleration of Large-Scale Wave Simulations
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218680openalex-snapshot
Exploiting Computation Reuse for Stencil Accelerators
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00032openalex-snapshot
Extending High-Level Synthesis for Task-Parallel Programs
inferred← citeshttps://doi.org/10.1109/iccke54056.2021.9721464openalex-snapshot
SASIAF, A Scalable Accelerator for Seismic Imaging on Amazon AWS FPGAs
inferred← citeshttps://doi.org/10.1109/tc.2023.3271060openalex-snapshot
DHTS: A Dynamic Hybrid Tiling Strategy for Optimizing Stencil Computation on GPUs
inferred← citeshttps://doi.org/10.1145/3431920.3439470openalex-snapshot
Extending High-Level Synthesis for Task-Parallel Programs
inferred← citeshttps://doi.org/10.11606/t.3.2021.tde-18052021-154710openalex-snapshot
ASLI schenes as a kernel convolved way to optimize stencil computation.
inferred← citeshttps://doi.org/10.70675/7954fab8ze891z46eeza55az2fc9177718dcopenalex-snapshot
Design space exploration of image processing algorithms on FPGAs
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.