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IPC Considered Harmful for Multiprocessor Workloads
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44587-0_1openalex-snapshot
SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/hpca.2003.1183520openalex-snapshot
Variability in architectural simulations of multi-threaded workloads
inferredcites →https://doi.org/10.1109/hpca.2005.8openalex-snapshot
Characterizing and Comparing Prevailing Simulation Techniques
inferredcites →https://doi.org/10.1109/l-ca.2004.6openalex-snapshot
Efficiently Evaluating Speedup Using Sampled Processor Simulation
inferredcites →https://doi.org/10.1109/mc.2003.1178046openalex-snapshot
Simulating a $2M commercial server on a $2K PC
inferredcites →https://doi.org/10.1109/micro.1998.742770openalex-snapshot
The YAGS branch prediction scheme
inferredcites →https://doi.org/10.1109/micro.2004.21openalex-snapshot
Managing Wire Delay in Large Chip-Multiprocessor Caches
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/pact.1996.552555openalex-snapshot
The effects of mispredicted-path execution on branch prediction structures
inferredcites →https://doi.org/10.1109/pact.2003.1238019openalex-snapshot
Redeeming IPC as a performance metric for multithreaded programs
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/277851.277897openalex-snapshot
Generating representative Web workloads for network and server performance evaluation
inferredcites →https://doi.org/10.1145/285930.285986openalex-snapshot
A characterization of processor performance in the VAX-11/780
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/773453.808199openalex-snapshot
A Characterization of Processor Performance in the vax-11/780
inferredcites →https://doi.org/10.1145/800015.808199openalex-snapshot
A Characterization of Processor Performance in the vax-11/780
inferredcites →https://doi.org/10.5555/290940.290962openalex-snapshot
The YAGS branch prediction scheme
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Cooperative Caching for Chip Multiprocessors
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Freeze'nSense: estimation of performance isolation in cloud environments
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Full-System Simulation from Embedded to High-Performance Systems
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Computer Architecture Performance Evaluation Methods
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Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
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Architectural Implications of Cache Coherence Protocols with Network Applications on Chip MultiProcessors
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SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs
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Research on Shared Resource Contention of Cloud Data Center
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S2MSim: Cycle-Accurate and High-Performance Simulator Based on Multi-Threading for Space Multi-Core Processor
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ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models
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Challenges of Reducing Cycle-accurate Simulation Time for TBP Applications
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MultiPoint: Enabling scalable pre-silicon performance evaluation for multi-task workloads
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inferred← citeshttps://doi.org/10.1051/epjconf/202429504027openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/access.2024.3354069openalex-snapshot
Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation
inferred← citeshttps://doi.org/10.1109/cloud.2015.35openalex-snapshot
VMcSim: A Detailed Manycore Simulator for Virtualized Systems
inferred← citeshttps://doi.org/10.1109/cloud55607.2022.00034openalex-snapshot
Radio: Reconciling Disk I/O Interference in a Para-virtualized Cloud
inferred← citeshttps://doi.org/10.1109/compsac.2018.00105openalex-snapshot
Measurement-Based Evaluation of Data-Parallelism for OpenCV Feature-Detection Algorithms
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586287openalex-snapshot
SmartBoost: Lightweight ML-Driven Boosting for Thermally-Constrained Many-Core Processors
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133176openalex-snapshot
Centralized Training and Decentralized Control through the Actor-Critic Paradigm for Highly Optimized Multicores
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Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer
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Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study
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In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522340openalex-snapshot
ESESC: A fast multicore simulator using Time-Based Sampling
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056061openalex-snapshot
Scaling distributed cache hierarchies through computation and data co-scheduling
inferred← citeshttps://doi.org/10.1109/hpca.2017.43openalex-snapshot
Maximizing Cache Performance Under Uncertainty
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00051openalex-snapshot
LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00091openalex-snapshot
Prosper: Program Stack Persistence in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00062openalex-snapshot
Efficient Caching with A Tag-enhanced DRAM
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408606openalex-snapshot
Nugget: Portable Program Snippets
inferred← citeshttps://doi.org/10.1109/hpcc-smartcity-dss.2016.0117openalex-snapshot
AHRC: An Optimized Cache Associativity
inferred← citeshttps://doi.org/10.1109/icdcs47774.2020.00050openalex-snapshot
Thread-Placement Learning
inferred← citeshttps://doi.org/10.1109/icpp.2015.44openalex-snapshot
Shorter On-Line Warmup for Sampled Simulation of Multi-threaded Applications
inferred← citeshttps://doi.org/10.1109/iiswc50251.2020.00019openalex-snapshot
CPI for Runtime Performance Measurement: The Good, the Bad, and the Ugly
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00031openalex-snapshot
SATORI: Efficient and Fair Resource Partitioning by Sacrificing Short-Term Benefits for Long-Term Gains
inferred← citeshttps://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferred← citeshttps://doi.org/10.1109/ispass.2013.6557141openalex-snapshot
Sampled simulation of multi-threaded applications
inferred← citeshttps://doi.org/10.1109/ispass.2014.6844456openalex-snapshot
BarrierPoint: Sampled simulation of multi-threaded applications
inferred← citeshttps://doi.org/10.1109/ispass64960.2025.00033openalex-snapshot
Use Equal-Work or Equal-Time Speedup, Not Geomean Speedup
inferred← citeshttps://doi.org/10.1109/ispass69572.2026.00025openalex-snapshot
Understanding Simulated Architecture via gem5 Call-Stack Profiling
inferred← citeshttps://doi.org/10.1109/iwqos.2015.7404740openalex-snapshot
Contention detection by throttling: A black-box on-line approach
inferred← citeshttps://doi.org/10.1109/lca.2024.3361925openalex-snapshot
R.I.P. Geomean Speedup Use Equal-Work (Or Equal-Time) Harmonic Mean Speedup Instead
inferred← citeshttps://doi.org/10.1109/mcsoc.2014.48openalex-snapshot
Adaptive V-Set Cache for Multi-core Processors
inferred← citeshttps://doi.org/10.1109/micro.2006.14openalex-snapshot
Coherence Ordering for Ring-based Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/micro.2010.20openalex-snapshot
The ZCache: Decoupling Ways and Associativity
inferred← citeshttps://doi.org/10.1109/micro.2016.7783737openalex-snapshot
Exploiting semantic commutativity in hardware speculation
inferred← citeshttps://doi.org/10.1109/micro.2018.00058openalex-snapshot
Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies
inferred← citeshttps://doi.org/10.1109/mm.2008.44openalex-snapshot
System-Level Performance Metrics for Multiprogram Workloads
inferred← citeshttps://doi.org/10.1109/paap.2010.50openalex-snapshot
Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/pact.2013.6618814openalex-snapshot
Transparent CPU-GPU collaboration for data-parallel kernels on heterogeneous systems
inferred← citeshttps://doi.org/10.1109/pact.2013.6618818openalex-snapshot
Meeting midway: improving CMP performance with memory-side prefetching
inferred← citeshttps://doi.org/10.1109/pact.2017.42openalex-snapshot
Nexus: A New Approach to Replication in Distributed Shared Caches
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SDM: Sharing-Enabled Disaggregated Memory System with Cache Coherent Compute Express Link
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TPE: XPU-Point: Simulator-Agnostic Sample Selection Methodology for Heterogeneous CPU-GPU Applications
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ARTE: An Application-specific Run-Time management framework for multi-core systems
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PAM: A novel performance/power aware meta-scheduler for multi-core systems
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On-Chip Network Evaluation Framework
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Measuring interference between live datacenter applications
inferred← citeshttps://doi.org/10.1109/tc.2011.199openalex-snapshot
Importance of Coherence Protocols with Network Applications on Multicore Processors
inferred← citeshttps://doi.org/10.1109/tc.2013.67openalex-snapshot
DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance
inferred← citeshttps://doi.org/10.1109/tc.2015.2389831openalex-snapshot
Multiprocessor Capacity Metric and Analysis
inferred← citeshttps://doi.org/10.1109/tc.2020.3023022openalex-snapshot
Neural Network-based Performance Prediction for Task Migration on S-NUCA Many-Cores
inferred← citeshttps://doi.org/10.1109/tc.2021.3112970openalex-snapshot
LFOC+: A Fair OS-level Cache-Clustering Policy for Commodity Multicore Systems
inferred← citeshttps://doi.org/10.1109/tcad.2009.2026357openalex-snapshot
Utilizing Predictors for Efficient Thermal Management in Multiprocessor SoCs
inferred← citeshttps://doi.org/10.1109/tmscs.2017.2701795openalex-snapshot
PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors
inferred← citeshttps://doi.org/10.1109/tpds.2015.2442983openalex-snapshot
Predicting Cross-Core Performance Interference on Multicore Processors with Regression Analysis
inferred← citeshttps://doi.org/10.1109/tsc.2017.2720742openalex-snapshot
Making Neighbors Quiet: An Approach to Detect Virtual Resource Contention
inferred← citeshttps://doi.org/10.1142/s0218126614500959openalex-snapshot
V-SET CACHE: AN EFFICIENT ADAPTIVE SHARED CACHE FOR MULTI-CORE PROCESSORS
inferred← citeshttps://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1145/1250662.1250670openalex-snapshot
Virtual hierarchies to support server consolidation
inferred← citeshttps://doi.org/10.1145/1273440.1250670openalex-snapshot
Virtual hierarchies to support server consolidation
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Characterization of Apache web server with Specweb2005
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In-network coherence filtering
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Run-time energy management of manycore systems through reconfigurable interconnects
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The impact of memory subsystem resource sharing on datacenter applications
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Scalable power control for many-core architectures running multi-threaded applications
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The impact of memory subsystem resource sharing on datacenter applications
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Scalable power control for many-core architectures running multi-threaded applications
inferred← citeshttps://doi.org/10.1145/2039370.2039404openalex-snapshot
Capacity metric for chip heterogeneous multiprocessors
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A systematic methodology to develop resilient cache coherence protocols
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Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication
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Dynamic adaptive virtual core mapping to improve power, energy, and performance in multi-socket multicores
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Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
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Empirical measurement of instruction level parallelism for four generations of ARM CPUs
inferred← citeshttps://doi.org/10.1145/2465529.2465756openalex-snapshot
Reuse-based online models for caches
inferred← citeshttps://doi.org/10.1145/2494232.2465756openalex-snapshot
Reuse-based online models for caches
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QoS-Aware scheduling in heterogeneous datacenters with paragon
inferred← citeshttps://doi.org/10.1145/2818353openalex-snapshot
Two-Level Hybrid Sampled Simulation of Multithreaded Applications
inferred← citeshttps://doi.org/10.1145/2830772.2830774openalex-snapshot
Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems
inferred← citeshttps://doi.org/10.1145/2967360.2967375openalex-snapshot
So many performance events, so little time
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Leveraging Caches to Accelerate Hash Tables and Memoization
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An Experimental Evaluation of Workload Driven DVFS
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PMU-Events-Driven DVFS Techniques for Improving Energy Efficiency of Modern Processors
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The Case of Unsustainable CPU Affinity
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ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage
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Pac-Sim: Simulation of Multi-threaded Workloads using Intelligent, Live Sampling
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A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices
inferred← citeshttps://doi.org/10.1145/3698365.3698371openalex-snapshot
The Case of Unsustainable CPU Affinity
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Accelerating the Simulation of Parallel Workloads using Loop-Bounded Checkpoints
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RDPart: A reuse-based OS-level cache-partitioning policy for fairness optimization in cloud data centers
inferred← citeshttps://doi.org/10.1166/jolpe.2014.1359openalex-snapshot
Message Passing-Aware Power Management on Many-Core Systems
inferred← citeshttps://doi.org/10.1177/10943420251348799openalex-snapshot
Technology trends in computing hardware and their impacts on high-performance scientific computing Part I: General-purpose processors and hardware accelerators
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A Learning-Based Framework Incorporating Domain Knowledge for Performance Modeling
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An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs
inferred← citeshttps://doi.org/10.2200/s00273ed1v01y201006cac010openalex-snapshot
Computer Architecture Performance Evaluation Methods
inferred← citeshttps://doi.org/10.26076/b7cb-073bopenalex-snapshot
Most Progress Made Algorithm: Combating Synchronization Induced Performance Loss on Salvaged Chip Multi-Processors
inferred← citeshttps://doi.org/10.35537/10915/62960openalex-snapshot
Optimización de rendimiento, justicia y consumo energético en sistemas multicore asimétricos mediante planificación
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Optimización de rendimiento, justicia y consumo energético en sistemas multicore asimétricos mediante planificación
inferred← citeshttps://doi.org/10.4304/jcp.7.1.53-64openalex-snapshot
Task Scheduling Based On Thread Essence and Resource Limitations
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Prediction in Projection: A new paradigm in delay-coordinate reconstruction
inferred← citeshttps://doi.org/10.4995/thesis/10251/6024openalex-snapshot
Efficient techniques to provide scalability for token-based cache coherence protocols.
inferred← citeshttps://doi.org/10.4995/thesis/10251/79551openalex-snapshot
Improving Energy and Area Scalability of the Cache Hierarchy in CMPs
inferred← citeshttps://doi.org/10.5121/ijcseit.2013.3201openalex-snapshot
Phase-Priority Based Directory Coherence for Multicore Processor
inferred← citeshttps://doi.org/10.5555/1413370.1413410openalex-snapshot
PAM: a novel performance/power aware meta-scheduler for multi-core systems
inferred← citeshttps://doi.org/10.5555/2388996.2389066openalex-snapshot
Measuring interference between live datacenter applications
inferred← citeshttps://doi.org/10.5555/2492708.2492755openalex-snapshot
Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer
inferred← citeshttps://doi.org/10.5555/2523721.2523746openalex-snapshot
SMT-centric power-aware thread placement in chip multiprocessors
inferred← citeshttps://doi.org/10.5555/2523721.2523752openalex-snapshot
Jigsaw: scalable software-defined caches
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HPC memory systems: Implications of system simulation and checkpointing
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Behavioral Application-dependent superscolor core modeling
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Finding, Measuring, and Reducing Inefficiencies in Contemporary Computer Systems
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