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Smart-Hop Arbitration Request Propagation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/hpca.2009.4798251openalex-snapshot
Express Cube Topologies for on-Chip Interconnects
inferredcites →https://doi.org/10.1109/hpca.2009.4798274openalex-snapshot
Prediction router: Yet another low latency on-chip router architecture
inferredcites →https://doi.org/10.1109/hpca.2013.6522334openalex-snapshot
Breaking the on-chip latency barrier using SMART
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/jetcas.2012.2193936openalex-snapshot
Swizzle-Switch Networks for Many-Core Systems
inferredcites →https://doi.org/10.1109/micro.2007.15openalex-snapshot
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/nocs.2012.31openalex-snapshot
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
inferredcites →https://doi.org/10.1109/tvlsi.2012.2211904openalex-snapshot
SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects
inferredcites →https://doi.org/10.1109/tvlsi.2016.2538284openalex-snapshot
Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network
inferredcites →https://doi.org/10.1145/165123openalex-snapshot
Proceedings of the 20th annual international symposium on Computer architecture - ISCA '93
inferredcites →https://doi.org/10.1145/2228360.2228431openalex-snapshot
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/asp-dac47756.2020.9045103openalex-snapshot
Contention Minimized Bypassing in SMART NoC
inferred← citeshttps://doi.org/10.1109/ce2ct64011.2025.10941326openalex-snapshot
Design and Development of Chip Design for Digital Electronic System: Evolution and Trends
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys53884.2021.00131openalex-snapshot
TLM-NoC: Two Level Mesh Network-on-Chip for Performance Improvement
inferred← citeshttps://doi.org/10.1109/ispass48437.2020.00015openalex-snapshot
BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass
inferred← citeshttps://doi.org/10.1109/tc.2021.3068615openalex-snapshot
S-SMART++: A Low-Latency NoC Leveraging Speculative Bypass Requests
inferred← citeshttps://doi.org/10.1109/tc.2021.3111517openalex-snapshot
Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes
inferred← citeshttps://doi.org/10.1109/tcad.2020.3015440openalex-snapshot
Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip
inferred← citeshttps://doi.org/10.1109/tcad.2021.3091961openalex-snapshot
ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission
inferred← citeshttps://doi.org/10.1109/tcad.2022.3151021openalex-snapshot
LAMP: Load-Balanced Multipath Parallel Transmission in Point-to-Point NoCs
inferred← citeshttps://doi.org/10.1145/3412841.3441895openalex-snapshot
Partial order based non-preemptive communication scheduling towards real-time networks-on-chip
inferred← citeshttps://doi.org/10.1145/3453688.3461521openalex-snapshot
Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCs
inferred← citeshttps://doi.org/10.1145/3476985openalex-snapshot
MARCO: A High-performance Task M apping a nd R outing Co -optimization Framework for Point-to-Point NoC-based Heterogeneous Computing Systems
inferred← citeshttps://doi.org/10.1145/3487018openalex-snapshot
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing
inferred← citeshttps://doi.org/10.1145/3631527openalex-snapshot
DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip
inferred← citeshttps://doi.org/10.1145/3833878openalex-snapshot
TOSCA: Towards Semi-Centralized Scheduling in Dataflow Architectures via Hardware-Software Co-Design
inferred← citeshttps://doi.org/10.3103/s0146411623040041openalex-snapshot
Scheduling Strategies and Future Directions for NoC: A Systematic Literature Review
inferred← citeshttps://doi.org/10.32657/10356/156762openalex-snapshot
Hardware-software co-design and optimization for point-to-point network-on-chip based many-core systems
inferred← citeshttps://doi.org/10.3390/mi14030501openalex-snapshot
PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs
inferred← citeshttps://doi.org/10.48550/arxiv.2011.09261openalex-snapshot
ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission
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