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https://doi.org/10.1145/3358177
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/j.micpro.2014.05.009openalex-snapshot
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric
inferredcites →https://doi.org/10.1023/a:1008069920230openalex-snapshot
Parametric Analysis of Polyhedral Iteration Spaces
inferredcites →https://doi.org/10.1109/12.859540openalex-snapshot
MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
inferredcites →https://doi.org/10.1109/cgo.2004.1281665openalex-snapshot
LLVM: a compilation framework for lifelong program analysis & transformation
inferredcites →https://doi.org/10.1109/dac.2018.8465833openalex-snapshot
DNestMap: Mapping Deeply-Nested Loops on Ultra-Low Power CGRAs
inferredcites →https://doi.org/10.1109/dac.2018.8465892openalex-snapshot
RAMP: Resource-Aware Mapping for CGRAs
inferredcites →https://doi.org/10.1109/euc.2014.26openalex-snapshot
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis
inferredcites →https://doi.org/10.1109/iccad.2017.8203842openalex-snapshot
SAT-based compilation to a non-vonNeumann processor
inferredcites →https://doi.org/10.1109/mdat.2015.2440413openalex-snapshot
A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller
inferredcites →https://doi.org/10.1109/tc.2016.2595560openalex-snapshot
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
inferredcites →https://doi.org/10.1109/tcad.2016.2611506openalex-snapshot
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip
inferredcites →https://doi.org/10.1109/tcad.2017.2693274openalex-snapshot
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays
inferredcites →https://doi.org/10.1109/tcsi.2016.2647322openalex-snapshot
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator
inferredcites →https://doi.org/10.1109/tpds.2017.2682241openalex-snapshot
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory
inferredcites →https://doi.org/10.1109/tvlsi.2015.2474129openalex-snapshot
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures
inferredcites →https://doi.org/10.1145/1508128.1508158openalex-snapshot
SPR
inferredcites →https://doi.org/10.1145/1755888.1755892openalex-snapshot
Operation and data mapping for CGRAs with multi-bank memory
inferredcites →https://doi.org/10.1145/192724.192731openalex-snapshot
Iterative modulo scheduling
inferredcites →https://doi.org/10.1145/2003695.2003702openalex-snapshot
Memory access optimization in compilation for coarse-grained reconfigurable architectures
inferredcites →https://doi.org/10.1145/2228360.2228600openalex-snapshot
EPIMap
inferredcites →https://doi.org/10.1145/2459316.2459319openalex-snapshot
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA
inferredcites →https://doi.org/10.1145/2463209.2488748openalex-snapshot
Memory partitioning for multidimensional arrays in high-level synthesis
inferredcites →https://doi.org/10.1145/2463209.2488756openalex-snapshot
REGIMap
inferredcites →https://doi.org/10.1145/2463209.2488757openalex-snapshot
Polyhedral model based mapping optimization of loop nests for CGRAs
inferredcites →https://doi.org/10.1145/2554688.2554780openalex-snapshot
Theory and algorithm for generalized memory partitioning in high-level synthesis
inferredcites →https://doi.org/10.1145/2656075.2656085openalex-snapshot
Flattening-based mapping of imperfect loop nests for CGRAs
inferredcites →https://doi.org/10.1145/2744769.2744831openalex-snapshot
Efficient memory partitioning for parallel data access in multidimensional arrays
inferredcites →https://doi.org/10.1145/2749469.2750390openalex-snapshot
Efficient execution of memory access phases using dataflow specialization
inferredcites →https://doi.org/10.1145/2966986.2967049openalex-snapshot
Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory
inferredcites →https://doi.org/10.1145/2966986.2967056openalex-snapshot
Multibank memory optimization for parallel data access in multiple data arrays
inferredcites →https://doi.org/10.1145/3061639.3062262openalex-snapshot
HyCUBE
inferredcites →https://doi.org/10.1145/3079856.3080255openalex-snapshot
Stream-Dataflow Acceleration
inferredcites →https://doi.org/10.1145/3203217.3203267openalex-snapshot
A decoupled access-execute architecture for reconfigurable accelerators
inferredcites →https://doi.org/10.5555/956417.956540openalex-snapshot
The Reconfigurable Streaming Vector Processor (RSVPTM)

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-39932-9_16openalex-snapshot
Pipelined CNN Inference on Heterogeneous Multi-processor System-on-Chip
inferred← citeshttps://doi.org/10.1007/978-981-15-6401-7_50-1openalex-snapshot
Coarse-Grained Reconfigurable Array (CGRA)
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_50openalex-snapshot
Coarse-Grained Reconfigurable Array (CGRA)
inferred← citeshttps://doi.org/10.1038/s41699-022-00325-5openalex-snapshot
Multilevel artificial electronic synaptic device of direct grown robust MoS2 based memristor array for in-memory deep neural network
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247862openalex-snapshot
DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133240openalex-snapshot
Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00061openalex-snapshot
DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00021openalex-snapshot
Mocarabe: High-Performance Time-Multiplexed Overlays for FPGAs
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00040openalex-snapshot
LISA: Graph Neural Network based Portable Mapping on Spatial Accelerators
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00015openalex-snapshot
E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping
inferred← citeshttps://doi.org/10.1109/icassp40776.2020.9054275openalex-snapshot
dMazeRunner: Optimizing Convolutions on Dataflow Accelerators
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00070openalex-snapshot
OpenCGRA: An Open-Source Unified Framework for Modeling, Testing, and Evaluating CGRAs
inferred← citeshttps://doi.org/10.1109/icecs58634.2023.10382797openalex-snapshot
Optimizing Data Availability and Utilization in Deep Learning Accelerator SoCs
inferred← citeshttps://doi.org/10.1109/icfpt56656.2022.9974339openalex-snapshot
Energy Efficient Design of Coarse-Grained Reconfigurable Architectures: Insights, Trends and Challenges
inferred← citeshttps://doi.org/10.1109/ipdpsw59300.2023.00075openalex-snapshot
Efficient Data Streaming for a Tightly-Coupled Coarse-Grained Reconfigurable Array
inferred← citeshttps://doi.org/10.1109/ipdpsw71298.2026.00099openalex-snapshot
Compiler-Based Performance Results for Regular Application Kernels on the HPC CGRA HiPReP
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00068openalex-snapshot
Lora: Towards Improved Applicability of Reconfigurable Architecture for Versatile Nonlinear Functions
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043426openalex-snapshot
Mage: a Decoupled Access-Execute CGRA tailored for Static Control Applications
inferred← citeshttps://doi.org/10.1109/sbac-pad66369.2025.00013openalex-snapshot
MIDAS: A Mapping Infrastructure for Configurable, Data-Streaming Based Domain Specific Accelerators
inferred← citeshttps://doi.org/10.1109/tcad.2020.3022015openalex-snapshot
CRIMSON: Compute-Intensive Loop Acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs
inferred← citeshttps://doi.org/10.1109/tcad.2021.3058313openalex-snapshot
ChordMap: Automated Mapping of Streaming Applications Onto CGRA
inferred← citeshttps://doi.org/10.1109/tcad.2022.3185544openalex-snapshot
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration
inferred← citeshttps://doi.org/10.1109/tcad.2024.3451978openalex-snapshot
Optimizing Data Reuse for Loop Mapping on CGRAs With Joint Affine and Nonaffine Transformations
inferred← citeshttps://doi.org/10.1109/tcad.2025.3630548openalex-snapshot
Data Transfer Optimization for Loop Mapping on CGRAs via Polyhedral Transformation
inferred← citeshttps://doi.org/10.1109/tcad.2025.3642732openalex-snapshot
Dependency-Aware Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring
inferred← citeshttps://doi.org/10.1145/3503222.3507772openalex-snapshot
REVAMP: a systematic framework for heterogeneous CGRA realization
inferred← citeshttps://doi.org/10.1145/3631118openalex-snapshot
Flip : Data-centric Edge CGRA Accelerator
inferred← citeshttps://doi.org/10.1145/3656642openalex-snapshot
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA
inferred← citeshttps://doi.org/10.1145/3658617.3697544openalex-snapshot
Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring
inferred← citeshttps://doi.org/10.1145/3663675openalex-snapshot
SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs
inferred← citeshttps://doi.org/10.1145/3669940.3707230openalex-snapshot
Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning
inferred← citeshttps://doi.org/10.1145/3676536.3676734openalex-snapshot
DISC: Exploiting Data Parallelism of Non-Stencil Computations on CGRAs via Dynamic Iteration Scheduling
inferred← citeshttps://doi.org/10.1145/3676536.3676777openalex-snapshot
Sustainable Hardware Specialization
inferred← citeshttps://doi.org/10.1145/3695880openalex-snapshot
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication
inferred← citeshttps://doi.org/10.1145/3708493.3712695openalex-snapshot
Compiler Support for Speculation in Decoupled Access/Execute Architectures
inferred← citeshttps://doi.org/10.1145/3760386openalex-snapshot
Re-thinking Memory-Bound Limitations in CGRAs
inferred← citeshttps://doi.org/10.1145/3769303openalex-snapshot
DPTM: An Adaptive Scheduler Design Utilizing Timeslot Matching and Release Methods for Concurrent and Multi-task Interleaved Pipelining-oriented CGRA
inferred← citeshttps://doi.org/10.1587/transinf.2025edp7224openalex-snapshot
PMA: A High-Performance and Low-Overhead Parallel Memory Architecture Utilizing Three-Dimensional Adaptive Memory Partitioning and Task-Driven Scheduling Method for MCMD-Based CGRA
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3855958/v1openalex-snapshot
WITHDRAWN: CGRA Implementation of HEVC Decoder Using Predictable Context Directed Pattern Matching With Efficient and Flexible Memory Architecture
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3855958/v2openalex-snapshot
WITHDRAWN: CGRA Implementation of HEVC Decoder Using Predictable Context Directed Pattern Matching With Efficient and Flexible Memory Architecture
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473916openalex-snapshot
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
inferred← citeshttps://doi.org/10.23919/date56975.2023.10137123openalex-snapshot
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures
inferred← citeshttps://doi.org/10.23919/date64628.2025.10992940openalex-snapshot
Monomorphism-Based CGRA Mapping Via Space and Time Decoupling
inferred← citeshttps://doi.org/10.3390/electronics10182210openalex-snapshot
Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA
inferred← citeshttps://doi.org/10.3390/electronics15091924openalex-snapshot
STORM: Hardware-Aware Tiny Transformer Co-Design for Low-Power Inertial Human Activity Recognition
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