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Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs

https://doi.org/10.1145/3358183
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1023/b:daem.0000003962.54165.5copenalex-snapshot
Performance Analysis of Arbitration Policies for SoC Communication Architectures
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/apccas.2008.4746123openalex-snapshot
A reconfigurable arbiter for SOC applications
inferredcites →https://doi.org/10.1109/apccas62602.2024openalex-snapshot
2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
inferredcites →https://doi.org/10.1109/aspdac.2007.357980openalex-snapshot
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses
inferredcites →https://doi.org/10.1109/date.2007.364577openalex-snapshot
An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip
inferredcites →https://doi.org/10.1109/date.2011.5763319openalex-snapshot
Priority division: A high-speed shared-memory bus arbitration with bounded latency
inferredcites →https://doi.org/10.1109/dsd.2014.105openalex-snapshot
Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures
inferredcites →https://doi.org/10.1109/emc.2010.5575754openalex-snapshot
MBBA: A Multi-Bandwidth Bus Arbiter for Hard Real-Time
inferredcites →https://doi.org/10.1109/etfa.2011.6059179openalex-snapshot
Predictable bus arbitration schemes for heterogeneous time-critical workloads running on multicore processors
inferredcites →https://doi.org/10.1109/iccd.2010.5647792openalex-snapshot
Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems
inferredcites →https://doi.org/10.1109/rtss.2016.010openalex-snapshot
A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs
inferredcites →https://doi.org/10.1109/tc.2015.2425889openalex-snapshot
Memory Bandwidth Management for Efficient Performance Isolation in Multi-Core Platforms
inferredcites →https://doi.org/10.1109/tcad.2015.2513673openalex-snapshot
A Survey and Evaluation of FPGA High-Level Synthesis Tools
inferredcites →https://doi.org/10.1109/tvlsi.2006.878210openalex-snapshot
The LOTTERYBUS on-chip communication architecture
inferredcites →https://doi.org/10.1109/tvlsi.2011.2178620openalex-snapshot
An Analytical Latency Model for Networks-on-Chip
inferredcites →https://doi.org/10.1109/vlsid.2006.10openalex-snapshot
A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks
inferredcites →https://doi.org/10.1145/2744769.2744879openalex-snapshot
On-chip interconnection network for accelerator-rich architectures
inferredcites →https://doi.org/10.4230/lipics.ecrts.2019.14openalex-snapshot
Dual Priority Scheduling is Not Optimal

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-45410-3_11openalex-snapshot
Application Design Issues
inferred← citeshttps://doi.org/10.1007/978-3-032-37218-5_34openalex-snapshot
Security Auditing for RISC-V SoCs via Process Mining
inferred← citeshttps://doi.org/10.1007/s11241-023-09405-1openalex-snapshot
Main sources of variability and non-determinism in AD software: taxonomy and prospects to handle them
inferred← citeshttps://doi.org/10.1007/s11241-025-09446-8openalex-snapshot
Toward predictable AI-based real-time systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2022.102683openalex-snapshot
Towards an energy-efficient quarter-clairvoyant mixed-criticality system
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218652openalex-snapshot
AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247840openalex-snapshot
Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1109/fccm48280.2020.00026openalex-snapshot
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
inferred← citeshttps://doi.org/10.1109/fpl68686.2025.00019openalex-snapshot
Multiplexer Optimizations for Virtex FPGAs
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643538openalex-snapshot
Aker: A Design and Verification Framework for Safe and Secure SoC Access Control
inferred← citeshttps://doi.org/10.1109/icemi52946.2021.9679610openalex-snapshot
Design of Hardware Acceleration System for Video Image Reconstruction Based on AXI Bus
inferred← citeshttps://doi.org/10.1109/iscas46773.2023.10181609openalex-snapshot
SS-AXI: Secure and Safe Access Control Mechanism for Multi-Tenant Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/rage62451.2024.00014openalex-snapshot
Towards Zero-Trust Hardware Architectures in Safety and Security Critical System-on-Chips
inferred← citeshttps://doi.org/10.1109/rtas48715.2020.000-3openalex-snapshot
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling
inferred← citeshttps://doi.org/10.1109/rtas52030.2021.00032openalex-snapshot
Latency Analysis of I/O Virtualization Techniques in Hypervisor-Based Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtas52030.2021.00046openalex-snapshot
Brief Industry Paper: AXI-InterconnectRT: Towards a Real-Time AXI-Interconnect for System-on-Chips
inferred← citeshttps://doi.org/10.1109/rtas68450.2026.00033openalex-snapshot
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoCs with Multi-Core DPUs
inferred← citeshttps://doi.org/10.1109/rtss49844.2020.00015openalex-snapshot
Pythia-MCS: Enabling Quarter-Clairvoyance in I/O-Driven Mixed-Criticality Systems
inferred← citeshttps://doi.org/10.1109/rtss52674.2021.00047openalex-snapshot
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms
inferred← citeshttps://doi.org/10.1109/rtss62706.2024.00024openalex-snapshot
ROTA-I/O: Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness
inferred← citeshttps://doi.org/10.1109/tc.2022.3179227openalex-snapshot
AXI-IC^{RT}: Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs
inferred← citeshttps://doi.org/10.1109/tc.2022.3214113openalex-snapshot
Serving Multi-DNN Workloads on FPGAs: A Coordinated Architecture, Scheduling, and Mapping Perspective
inferred← citeshttps://doi.org/10.1109/tc.2022.3214117openalex-snapshot
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs
inferred← citeshttps://doi.org/10.1109/tc.2025.3584530openalex-snapshot
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
inferred← citeshttps://doi.org/10.1109/tcad.2022.3197343openalex-snapshot
Cut and Forward: Safe and Secure Communication for FPGA System on Chips
inferred← citeshttps://doi.org/10.1109/tcad.2023.3288511openalex-snapshot
NPRC-I/O: An NoC-Based Real-Time I/O System With Reduced Contention and Enhanced Predictability
inferred← citeshttps://doi.org/10.1109/tcad.2025.3528355openalex-snapshot
Superscalar Time-Triggered Versatile-Tensor Accelerator
inferred← citeshttps://doi.org/10.1109/tcad.2026.3652879openalex-snapshot
MCS 3 : A Mixed-Criticality System With Suspension-Awareness and Semi-Clairvoyance for Edge Computing
inferred← citeshttps://doi.org/10.1109/tpds.2024.3513416openalex-snapshot
Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-Based Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1145/3576914.3587508openalex-snapshot
Automated Generation, Verification, and Ranking of Secure SoC Access Control Policies
inferred← citeshttps://doi.org/10.1145/3607890openalex-snapshot
Proceedings of the International Conference on Embedded Software
inferred← citeshttps://doi.org/10.1145/3607890.3608457openalex-snapshot
Work-in-Progress: Flexible bus arbitration in mixed criticality systems
inferred← citeshttps://doi.org/10.1145/3607890.3608467openalex-snapshot
Work-in-Progress: mixing computation and interaction on FPGA
inferred← citeshttps://doi.org/10.1145/3672608.3707822openalex-snapshot
On the Time Predictability of AXI4
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473925openalex-snapshot
Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774768openalex-snapshot
Understanding and Mitigating Memory Interference in FPGA-based HeSoCs
inferred← citeshttps://doi.org/10.23919/date58400.2024.10546511openalex-snapshot
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs
inferred← citeshttps://doi.org/10.23919/date64628.2025.10992968openalex-snapshot
Xray: Detecting and Exploiting Vulnerabilities in Arm AXI Interconnects
inferred← citeshttps://doi.org/10.3390/mi11121063openalex-snapshot
A Bandwidth Control Arbitration for SoC Interconnections Performing Applications with Task Dependencies
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