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Unrolling Ternary Neural Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-46493-0_32openalex-snapshot
XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks
inferredcites →https://doi.org/10.1007/978-3-319-70096-0_41openalex-snapshot
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks
inferredcites →https://doi.org/10.1016/j.neucom.2017.09.046openalex-snapshot
FP-BNN: Binarized neural network on FPGA
inferredcites →https://doi.org/10.1109/icassp.2017.7952679openalex-snapshot
Accelerating Deep Convolutional Networks using low-precision and sparsity
inferredcites →https://doi.org/10.1109/icecs.2018.8617860openalex-snapshot
Constant Matrix Multiplication with Ternary Adders
inferredcites →https://doi.org/10.1109/ipdpsw.2018.00032openalex-snapshot
Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform
inferredcites →https://doi.org/10.1109/iscas.2012.6272072openalex-snapshot
Pipelined adder graph optimization for high speed multiple constant multiplication
inferredcites →https://doi.org/10.1109/jssc.2016.2616357openalex-snapshot
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/sips.2016.54openalex-snapshot
Serving 22 Users in Real-Time with a 128-Antenna Massive MIMO Testbed
inferredcites →https://doi.org/10.1109/sips.2017.8110021openalex-snapshot
Structured sparse ternary weight coding of deep neural networks for efficient hardware implementations
inferredcites →https://doi.org/10.1109/socc.2017.8226056openalex-snapshot
FPGA-based CNN inference accelerator synthesized from multi-threaded C software
inferredcites →https://doi.org/10.1109/tassp.1984.1164433openalex-snapshot
Some complexity issues in digital signal processing
inferredcites →https://doi.org/10.1109/tc.2017.2701365openalex-snapshot
Optimization of Constant Matrix Multiplication with Low Power and High Throughput
inferredcites →https://doi.org/10.1109/tcad.2017.2682138openalex-snapshot
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration
inferredcites →https://doi.org/10.1109/tcsi.2005.859052openalex-snapshot
Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations
inferredcites →https://doi.org/10.1145/2847263.2847265openalex-snapshot
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/3020078.3021727openalex-snapshot
Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System
inferredcites →https://doi.org/10.1145/3020078.3021786openalex-snapshot
A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only)
inferredcites →https://doi.org/10.1145/3029580.3029586openalex-snapshot
Scaling Binarized Neural Networks on Reconfigurable Logic
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3140659.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.23919/fpl.2017.8056823openalex-snapshot
High performance binary neural networks on the Xeon+FPGA™ platform
inferredcites →https://doi.org/10.23919/fpl.2017.8056850openalex-snapshot
Scalable high-performance architecture for convolutional ternary neural networks on FPGA
inferredcites →https://doi.org/10.48550/arxiv.1602.02830openalex-snapshot
Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1
inferredcites →https://doi.org/10.48550/arxiv.1606.06160openalex-snapshot
DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients
inferredcites →https://doi.org/10.48550/arxiv.1705.01462openalex-snapshot
Ternary Neural Networks with Fine-Grained Quantization
inferredcites →https://doi.org/10.57702/zp44cu3gopenalex-snapshot
Learning Multiple Layers of Features from Tiny Images
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices
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Arithmetic for Deep Learning
inferred← citeshttps://doi.org/10.1016/j.egyr.2022.02.166openalex-snapshot
A novel sky image-based solar irradiance nowcasting model with convolutional block attention mechanism
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102198openalex-snapshot
In-circuit tuning of deep learning designs
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102257openalex-snapshot
Accelerating DNNs from local to virtualized FPGA in the Cloud: A survey of trends
inferred← citeshttps://doi.org/10.1109/access.2024.3409180openalex-snapshot
Efficient Hardware Design of DNN for RF Signal Modulation Recognition Employing Ternary Weights
inferred← citeshttps://doi.org/10.1109/access.2026.3720662openalex-snapshot
A Ternary Hybrid Perceptron Branch Predictor for Ternary Pipelined Architectures
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00055openalex-snapshot
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00057openalex-snapshot
Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs
inferred← citeshttps://doi.org/10.1109/fpl64840.2024.00030openalex-snapshot
Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision
inferred← citeshttps://doi.org/10.1109/fpl68686.2025.00016openalex-snapshot
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
inferred← citeshttps://doi.org/10.1109/iccmc65190.2025.11140776openalex-snapshot
Logic Network Circuits for Neural network Realization in Machine Learning Application using Graphene Nano Ribbon Field Effect Transistors
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00052openalex-snapshot
Real-Time Automatic Modulation Classification
inferred← citeshttps://doi.org/10.1109/icfpt52863.2021.9609847openalex-snapshot
Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator
inferred← citeshttps://doi.org/10.1109/icfpt64416.2024.11113475openalex-snapshot
Optimizing DNN Accelerator Compression Using Tolerable Accuracy Loss
inferred← citeshttps://doi.org/10.1109/ieeeconf67917.2025.11443855openalex-snapshot
Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators
inferred← citeshttps://doi.org/10.1109/ipdpsw50202.2020.00021openalex-snapshot
Real-time Automatic Modulation Classification using RFSoC
inferred← citeshttps://doi.org/10.1109/jetcas.2021.3129415openalex-snapshot
A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference
inferred← citeshttps://doi.org/10.1109/jetcas.2024.3389660openalex-snapshot
Low Latency Variational Autoencoder on FPGAs
inferred← citeshttps://doi.org/10.1109/jsen.2021.3062442openalex-snapshot
AVNC: Attention-Based VGG-Style Network for COVID-19 Diagnosis by CBAM
inferred← citeshttps://doi.org/10.1109/les.2023.3323635openalex-snapshot
Common Subexpression-Based Compression and Multiplication of Sparse Constant Matrices
inferred← citeshttps://doi.org/10.1109/tcad.2022.3183547openalex-snapshot
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation
inferred← citeshttps://doi.org/10.1109/tetc.2020.3026179openalex-snapshot
Nonvolatile Associative Memory Design Based on Spintronic Synapses and CNTFET Neurons
inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3055983openalex-snapshot
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register
inferred← citeshttps://doi.org/10.1109/tvlsi.2024.3504513openalex-snapshot
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution
inferred← citeshttps://doi.org/10.1145/3507698openalex-snapshot
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud
inferred← citeshttps://doi.org/10.1145/3587095openalex-snapshot
Resource-Efficient Convolutional Networks: A Survey on Model-, Arithmetic-, and Implementation-Level Techniques
inferred← citeshttps://doi.org/10.1145/3795794openalex-snapshot
MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration
inferred← citeshttps://doi.org/10.3390/math13071104openalex-snapshot
Detection of Surface Defects of Barrel Media Based on PaE-VGG Model
inferred← citeshttps://doi.org/10.48550/arxiv.2106.12840openalex-snapshot
NN2CAM: Automated Neural Network Mapping for Multi-Precision Edge Processing on FPGA-Based Cameras
inferred← citeshttps://doi.org/10.70675/ce233682z21c8z4566zb3c2ze14c05722e87openalex-snapshot
Conception d’une plate-forme multi-FPGAs dans le cloud pour les applications de réseaux de neurones
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