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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-78890-6_5openalex-snapshot
SqueezeJet: High-Level Synthesis Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1016/s0262-4079(16)30458-4openalex-snapshot
Machine outsmarts man in battle of the decade
inferredcites →https://doi.org/10.1038/nature14236openalex-snapshot
Human-level control through deep reinforcement learning
inferredcites →https://doi.org/10.1109/cvpr.2014.220openalex-snapshot
DeepFace: Closing the Gap to Human-Level Performance in Face Verification
inferredcites →https://doi.org/10.1109/isca.2016.40openalex-snapshot
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/tcsi.2017.2698019openalex-snapshot
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
inferredcites →https://doi.org/10.1109/tetc.2016.2554318openalex-snapshot
Runtime Support for Multiple Offload-Based Programming Models on Clustered Manycore Accelerators
inferredcites →https://doi.org/10.1109/tvlsi.2017.2654506openalex-snapshot
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
inferredcites →https://doi.org/10.1145/2597917.2597922openalex-snapshot
Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2847263.2847265openalex-snapshot
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Applying AI in Practice: Key Challenges and Lessons Learned
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Task-Specific Automation in Deep Learning Processes
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New paradigm of FPGA-based computational intelligence from surveying the implementation of DNN accelerators
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Survey of convolutional neural network accelerators on field-programmable gate array platforms: architectures and optimization techniques
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FPGA validated RISC V system on chip with a custom systolic array accelerator for edge AI inference
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Research on ZYNQ neural network acceleration method for aluminum surface microdefects
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Dynamic FPGA reconfiguration for scalable embedded artificial intelligence (AI): A co-design methodology for convolutional neural networks (CNN) acceleration
inferred← citeshttps://doi.org/10.1016/j.future.2026.108860openalex-snapshot
Memory-aware scheduling of AI workloads on a Messaging-based vector processing unit
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A time domain 2D OaA-based convolutional neural networks accelerator
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CoNNa–Hardware accelerator for compressed convolutional neural networks
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Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project
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Towards large-scale single-shot millimeter-wave imaging for low-cost security inspection
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GAHLS: an optimized graph analytics based high level synthesis framework
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Atmospheric neutron single event effects for multiple convolutional neural networks based on 28-nm and 16-nm SoC
inferred← citeshttps://doi.org/10.1098/rsta.2019.0155openalex-snapshot
PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors
inferred← citeshttps://doi.org/10.1109/access.2019.2956841openalex-snapshot
A Novel Software-Defined Convolutional Neural Networks Accelerator
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CPU-Accelerator Co-Scheduling for CNN Acceleration at the Edge
inferred← citeshttps://doi.org/10.1109/access.2020.3046730openalex-snapshot
Tracking In-Cabin Astronauts Using Deep Learning and Head Motion Clues
inferred← citeshttps://doi.org/10.1109/access.2021.3115243openalex-snapshot
ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge
inferred← citeshttps://doi.org/10.1109/aieee48629.2019.8977065openalex-snapshot
Synchronization of AXI Streaming Interfaces for Convolution Core Implementation on FPGA
inferred← citeshttps://doi.org/10.1109/cac57257.2022.10055526openalex-snapshot
Design an Efficient DNN Inference Framework with PS-PL Synergies in FPGA for Edge Computing
inferred← citeshttps://doi.org/10.1109/dasip48288.2019.9049213openalex-snapshot
CNN hardware acceleration on a low-power and low-cost APSoC
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Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project
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A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment
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A Systematic Assessment of Embedded Neural Networks for Object Detection
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HW/SW Co-Design of Cost-Efficient CNN Inference for Cognitive IoT
inferred← citeshttps://doi.org/10.1109/icfpt52863.2021.9609813openalex-snapshot
StreamSVD: Low-rank Approximation and Streaming Accelerator Co-design
inferred← citeshttps://doi.org/10.1109/icm.2018.8704093openalex-snapshot
Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project
inferred← citeshttps://doi.org/10.1109/ivs.2019.8814001openalex-snapshot
CNN-based Object Detection on Low Precision Hardware: Racing Car Case Study
inferred← citeshttps://doi.org/10.1109/jetcas.2020.3014503openalex-snapshot
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators
inferred← citeshttps://doi.org/10.1109/les.2019.2947312openalex-snapshot
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge
inferred← citeshttps://doi.org/10.1109/meco.2019.8760160openalex-snapshot
Age & Gender Classifier for Edge Computing
inferred← citeshttps://doi.org/10.1109/ojsscs.2022.3210082openalex-snapshot
DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training
inferred← citeshttps://doi.org/10.1109/sbcci55532.2022.9893223openalex-snapshot
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments
inferred← citeshttps://doi.org/10.1109/sbesc65055.2024.10771920openalex-snapshot
An Automatic Framework for Collaborative CPU Thread Throttling and FPGA HLS-Versioning
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CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL
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INCAME: Interruptible CNN Accelerator for Multirobot Exploration
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A Comprehensive Memory Management Framework for CPU-FPGA Heterogenous SoCs
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A Mixed-Pruning Based Framework for Embedded Convolutional Neural Network Acceleration
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Dilate-Invariant Temporal Convolutional Network for Real-Time Edge Applications
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CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets
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Eyelet: A Cross-Mesh NoC-Based Fine-Grained Sparse CNN Accelerator for Spatio-Temporal Parallel Computing Optimization
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A Survey of Deep Learning on CPUs: Opportunities and Co-Optimizations
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Optimization and deployment of CNNs at the edge
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Muon–Electron Pulse Shape Discrimination for Water Cherenkov Detectors Based on FPGA/SoC
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Edge Real-Time Object Detection and DPU-Based Hardware Implementation for Optical Remote Sensing Images
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An FPGA-Based Resource-Saving Hardware Accelerator for Deep Neural Network
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