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Flextended Tiles

https://doi.org/10.1145/3369382
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf01379404openalex-snapshot
Some efficient solutions to the affine scheduling problem. Part II. Multidimensional time
inferredcites →https://doi.org/10.1109/dmcc.1990.555436openalex-snapshot
The Triangle Method for Saving Startup Time in Parallel Computers
inferredcites →https://doi.org/10.1109/icpp.2005.2openalex-snapshot
Proceedings. 2005 International Conference on Parallel Processing
inferredcites →https://doi.org/10.1109/icpp.2009.44openalex-snapshot
Mapping the FDTD Application to Many-Core Chip Architectures
inferredcites →https://doi.org/10.1109/icpp.2011.47openalex-snapshot
Cache Accurate Time Skewing in Iterative Stencil Computations
inferredcites →https://doi.org/10.1109/sc.2012.107openalex-snapshot
Tiling stencil computations to maximize parallelism
inferredcites →https://doi.org/10.1109/tpds.2002.1003856openalex-snapshot
Automatic partitioning of parallel loops with parallelepiped-shaped tiles
inferredcites →https://doi.org/10.1109/tpds.2016.2615094openalex-snapshot
Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations
inferredcites →https://doi.org/10.1137/130935781openalex-snapshot
Modeling the Performance of Geometric Multigrid Stencils on Multicore Computer Architectures
inferredcites →https://doi.org/10.1142/s0129626414410023openalex-snapshot
The Relation Between Diamond Tiling and Hexagonal Tiling
inferredcites →https://doi.org/10.1145/1250734.1250761openalex-snapshot
Effective automatic parallelization of stencil computations
inferredcites →https://doi.org/10.1145/1275808.1276506openalex-snapshot
Real-time edge-aware image processing with the bilateral grid
inferredcites →https://doi.org/10.1145/1362622.1362691openalex-snapshot
Multi-level tiling
inferredcites →https://doi.org/10.1145/1375581.1375595openalex-snapshot
A practical automatic polyhedral parallelizer and locality optimizer
inferredcites →https://doi.org/10.1145/183432.183525openalex-snapshot
Static analysis of upper and lower bounds on dependences and parallelism
inferredcites →https://doi.org/10.1145/197405.197406openalex-snapshot
Compiler transformations for high-performance computing
inferredcites →https://doi.org/10.1145/2185520.2185528openalex-snapshot
Decoupling algorithms from schedules for easy optimization of image processing pipelines
inferredcites →https://doi.org/10.1145/2259016.2259044openalex-snapshot
Hierarchical overlapped tiling
inferredcites →https://doi.org/10.1145/2304576.2304619openalex-snapshot
High-performance code generation for stencil computations on GPU architectures
inferredcites →https://doi.org/10.1145/2400682.2400713openalex-snapshot
Polyhedral parallel code generation for CUDA
inferredcites →https://doi.org/10.1145/245.247openalex-snapshot
A multiresolution spline with application to image mosaics
inferredcites →https://doi.org/10.1145/2458523.2458526openalex-snapshot
Split tiling for GPUs
inferredcites →https://doi.org/10.1145/2491956.2462176openalex-snapshot
Halide
inferredcites →https://doi.org/10.1145/2544137.2544160openalex-snapshot
Hybrid Hexagonal/Classical Tiling for GPUs
inferredcites →https://doi.org/10.1145/2628071.2628092openalex-snapshot
OpenTuner
inferredcites →https://doi.org/10.1145/2628071.2628106openalex-snapshot
Tiling and optimizing time-iterated computations on periodic domains
inferredcites →https://doi.org/10.1145/2629645openalex-snapshot
Fast Local Laplacian Filters
inferredcites →https://doi.org/10.1145/2687414openalex-snapshot
Optimal Parallelogram Selection for Hierarchical Tiling
inferredcites →https://doi.org/10.1145/2694344.2694364openalex-snapshot
PolyMage
inferredcites →https://doi.org/10.1145/2723694openalex-snapshot
Local Laplacian filters
inferredcites →https://doi.org/10.1145/2739047openalex-snapshot
An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations
inferredcites →https://doi.org/10.1145/2743016openalex-snapshot
Polyhedral AST Generation Is More Than Scanning Polyhedra
inferredcites →https://doi.org/10.1145/2897824.2925952openalex-snapshot
Automatically scheduling halide image processing pipelines
inferredcites →https://doi.org/10.1145/3155290openalex-snapshot
Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations
inferredcites →https://doi.org/10.1145/3168832openalex-snapshot
Transforming loop chains via macro dataflow graphs
inferredcites →https://doi.org/10.1145/3178372.3179507openalex-snapshot
Modeling the conflicting demands of parallelism and Temporal/Spatial locality in affine scheduling
inferredcites →https://doi.org/10.1561/0600000020openalex-snapshot
Bilateral Filtering: Theory and Applications
inferredcites →https://doi.org/10.5244/c.2.23openalex-snapshot
A Combined Corner and Edge Detector

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s10766-022-00734-5openalex-snapshot
A Methodology for Efficient Tile Size Selection for Affine Loop Kernels
inferred← citeshttps://doi.org/10.1007/s11227-021-03835-zopenalex-snapshot
Revisiting split tiling for stencil computations in polyhedral compilation
inferred← citeshttps://doi.org/10.1051/bioconf/20249700021openalex-snapshot
Enhancing Programs Efficiency through a Machine Learning-Based Model for Tile Size Selection
inferred← citeshttps://doi.org/10.1109/access.2023.3345660openalex-snapshot
SlidingConv: Domain-Specific Description of Sliding Discrete Cosine Transform Convolution for Halide
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00044openalex-snapshot
Optimizing the Memory Hierarchy by Compositing Automatic Transformations on Computations and Data
inferred← citeshttps://doi.org/10.1109/tc.2023.3271060openalex-snapshot
DHTS: A Dynamic Hybrid Tiling Strategy for Optimizing Stencil Computation on GPUs
inferred← citeshttps://doi.org/10.1145/3410463.3414637openalex-snapshot
Bandwidth-Aware Loop Tiling for DMA-Supported Scratchpad Memory
inferred← citeshttps://doi.org/10.1145/3410463.3414649openalex-snapshot
Model-Based Warp Overlapped Tiling for Image Processing Programs on GPUs
inferred← citeshttps://doi.org/10.1145/3447818.3460369openalex-snapshot
Tile size selection of affine programs for GPGPUs using polyhedral cross-compilation
inferred← citeshttps://doi.org/10.1145/3453483.3454106openalex-snapshot
AKG: automatic kernel generation for neural processing units using polyhedral transformations
inferred← citeshttps://doi.org/10.1145/3635305openalex-snapshot
Modeling the Interplay between Loop Tiling and Fusion in Optimizing Compilers Using Affine Relations
inferred← citeshttps://doi.org/10.1145/3706107openalex-snapshot
StreamNet++: Memory-Efficient Streaming TinyML Model Compilation on Microcontrollers
inferred← citeshttps://doi.org/10.14529/cmse210303openalex-snapshot
An Approach to Extimate the Locality of Grained Computation Processes Organized to a Two-dimensional Structure
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