On the public citation graph

Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations

https://doi.org/10.1145/3155290
0 signed · 72 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/cpe.3180openalex-snapshot
Exploring performance and power properties of modern multi‐core chips via simple machine models
inferredcites →https://doi.org/10.1007/978-3-319-09873-9_8openalex-snapshot
Multi-Objective Auto-Tuning with Insieme: Optimization and Trade-Off Analysis for Time, Energy and Resource Usage
inferredcites →https://doi.org/10.1007/978-3-319-10214-6_12openalex-snapshot
Multi Objective Optimization of HPC Kernels for Performance, Power, and Energy
inferredcites →https://doi.org/10.1007/978-3-319-32149-3_7openalex-snapshot
Performance Analysis of the Kahan-Enhanced Scalar Product on Current Multicore Processors
inferredcites →https://doi.org/10.1007/978-3-642-14390-8_64openalex-snapshot
Introducing a Performance Model for Bandwidth-Limited Loop Kernels
inferredcites →https://doi.org/10.1007/978-3-642-19595-2_6openalex-snapshot
Locality Optimization of Stencil Applications Using Data Dependency Graphs
inferredcites →https://doi.org/10.1016/0167-8191(89)90100-2openalex-snapshot
: A parameter to characterize memory and communication bottlenecks
inferredcites →https://doi.org/10.1016/0743-7315(88)90002-0openalex-snapshot
Estimating interlock and improving balance for pipelined architectures
inferredcites →https://doi.org/10.1016/j.jocs.2011.01.010openalex-snapshot
Efficient multicore-aware parallelization strategies for iterative stencil computations
inferredcites →https://doi.org/10.1109/compsac.2009.82openalex-snapshot
Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization
inferredcites →https://doi.org/10.1109/icpp.2009.44openalex-snapshot
Mapping the FDTD Application to Many-Core Chip Architectures
inferredcites →https://doi.org/10.1109/icpp.2011.47openalex-snapshot
Cache Accurate Time Skewing in Iterative Stencil Computations
inferredcites →https://doi.org/10.1109/ipdps.2011.70openalex-snapshot
PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures
inferredcites →https://doi.org/10.1109/ipdps.2013.77openalex-snapshot
A Roofline Model of Energy
inferredcites →https://doi.org/10.1109/ipdpsw.2015.70openalex-snapshot
An Energy Efficiency Feature Survey of the Intel Haswell Processor
inferredcites →https://doi.org/10.1109/mcse.2013.95openalex-snapshot
Exascale Computing Trends: Adjusting to the "New Normal"' for Computer Architecture
inferredcites →https://doi.org/10.1109/sc.2010.2openalex-snapshot
3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs
inferredcites →https://doi.org/10.1109/sc.2012.107openalex-snapshot
Tiling stencil computations to maximize parallelism
inferredcites →https://doi.org/10.1109/sffcs.1999.814600openalex-snapshot
Cache-oblivious algorithms
inferredcites →https://doi.org/10.1137/070693199openalex-snapshot
Optimization and Performance Modeling of Stencil Computations on Modern Microprocessors
inferredcites →https://doi.org/10.1137/130935781openalex-snapshot
Modeling the Performance of Geometric Multigrid Stencils on Multicore Computer Architectures
inferredcites →https://doi.org/10.1137/140991133openalex-snapshot
Multicore-Optimized Wavefront Diamond Blocking for Optimizing Stencil Updates
inferredcites →https://doi.org/10.1142/s0129626410000296openalex-snapshot
LEVERAGING SHARED CACHES FOR PARALLEL TEMPORAL BLOCKING OF STENCIL CODES ON MULTICORE PROCESSORS AND CLUSTERS
inferredcites →https://doi.org/10.1142/s0129626414410023openalex-snapshot
The Relation Between Diamond Tiling and Hexagonal Tiling
inferredcites →https://doi.org/10.1145/1088149.1088197openalex-snapshot
Cache oblivious stencil computations
inferredcites →https://doi.org/10.1145/1379022.1375595openalex-snapshot
A practical automatic polyhedral parallelizer and locality optimizer
inferredcites →https://doi.org/10.1145/1498765.1498785openalex-snapshot
Roofline
inferredcites →https://doi.org/10.1145/17356.17362openalex-snapshot
Memory requirements for balanced computer architectures
inferredcites →https://doi.org/10.1145/1810085.1810096openalex-snapshot
Cache oblivious parallelograms in iterative stencil computations
inferredcites →https://doi.org/10.1145/1989493.1989508openalex-snapshot
The pochoir stencil compiler
inferredcites →https://doi.org/10.1145/2464996.2467268openalex-snapshot
A stencil compiler for short-vector SIMD architectures
inferredcites →https://doi.org/10.1145/2544137.2544160openalex-snapshot
Hybrid Hexagonal/Classical Tiling for GPUs
inferredcites →https://doi.org/10.1145/2751205.2751223openalex-snapshot
MODESTO
inferredcites →https://doi.org/10.1145/2751205.2751224openalex-snapshot
Optimizing Overlapped Memory Accesses in User-directed Vectorization
inferredcites →https://doi.org/10.1145/2751205.2751240openalex-snapshot
Quantifying Performance Bottlenecks of Stencil Computations Using the Execution-Cache-Memory Model
inferredcites →https://doi.org/10.1145/3155290openalex-snapshot
Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations
inferredcites →https://doi.org/10.1145/360827.360844openalex-snapshot
The parallel execution of DO loops
inferredcites →https://doi.org/10.1177/1094342012444795openalex-snapshot
Optimizing the performance of streaming numerical kernels on the IBM Blue Gene/P PowerPC 450 processor

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-50743-5_21openalex-snapshot
Understanding HPC Benchmark Performance on Intel Broadwell and Cascade Lake Processors
inferred← citeshttps://doi.org/10.1007/978-3-030-81691-9_10openalex-snapshot
Functionally Arranged Data for Algorithms with Space-Time Wavefront
inferred← citeshttps://doi.org/10.1109/cgo51591.2021.9370316openalex-snapshot
YaskSite: Stencil Optimization Techniques Applied to Explicit ODE Methods on Modern Architectures
inferred← citeshttps://doi.org/10.1109/cluster.2019.8891054openalex-snapshot
Asynchronous Task-Based Execution of the Reverse Time Migration for the Oil and Gas Industry
inferred← citeshttps://doi.org/10.1109/ipdps.2016.87openalex-snapshot
Optimization of an Electromagnetics Code with Multicore Wavefront Diamond Blocking and Multi-dimensional Intra-Tile Parallelization
inferred← citeshttps://doi.org/10.1109/sc41404.2022.00035openalex-snapshot
Scalable Distributed High-Order Stencil Computations
inferred← citeshttps://doi.org/10.1109/sc41406.2024.00059openalex-snapshot
LoRAStencil: Low-Rank Adaptation of Stencil Computation on Tensor Cores
inferred← citeshttps://doi.org/10.1109/tpds.2016.2615094openalex-snapshot
Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations
inferred← citeshttps://doi.org/10.1109/tpds.2018.2826533openalex-snapshot
Optimizations of Unstructured Aerodynamics Computations for Many-core Architectures
inferred← citeshttps://doi.org/10.1109/tpds.2022.3223512openalex-snapshot
Level-Based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication
inferred← citeshttps://doi.org/10.1117/12.2312545openalex-snapshot
Efficient optical simulation of nano structures in thin-film solar cells
inferred← citeshttps://doi.org/10.1137/23m1625962openalex-snapshot
Smoothers with Localized Residual Computations for Geometric Multigrid Methods for Higher-Order Finite Elements
inferred← citeshttps://doi.org/10.1145/3126908.3126920openalex-snapshot
Tessellating stencils
inferred← citeshttps://doi.org/10.1145/3165280openalex-snapshot
Quasi-matrix-free Hybrid Multigrid on Dynamically Adaptive Cartesian Grids
inferred← citeshttps://doi.org/10.1145/3168824openalex-snapshot
High performance stencil code generation with Lift
inferred← citeshttps://doi.org/10.1145/3303117.3306172openalex-snapshot
Multi-dimensional Vectorization in LLVM
inferred← citeshttps://doi.org/10.1145/3337821.3337835openalex-snapshot
Tessellating Star Stencils
inferred← citeshttps://doi.org/10.1145/3368858openalex-snapshot
Tiling Optimizations for Stencil Computations Using Rewrite Rules in L ift
inferred← citeshttps://doi.org/10.1145/3369382openalex-snapshot
Flextended Tiles
inferred← citeshttps://doi.org/10.1145/3458817.3476154openalex-snapshot
Reducing redundancy in data organization and arithmetic calculation for stencil computations
inferred← citeshttps://doi.org/10.1145/3470637openalex-snapshot
Efficient Parallel 3D Computation of the Compressible Euler Equations with an Invariant-domain Preserving Second-order Finite-element Scheme
inferred← citeshttps://doi.org/10.1145/3659914.3659936openalex-snapshot
Leveraging the High Bandwidth of Last-Level Cache for HPC Seismic Imaging Applications
inferred← citeshttps://doi.org/10.1145/3797905.3807849openalex-snapshot
WindStencil: Unleashing GPU Potential for High-Order Stencil Computation in High-Performance Inviscid CFD Simulations
inferred← citeshttps://doi.org/10.1177/1094342020923027openalex-snapshot
Asynchronous computations for solving the acoustic wave propagation equation
inferred← citeshttps://doi.org/10.1177/1094342020959423openalex-snapshot
A domain-specific language and matrix-free stencil code for investigating electronic properties of Dirac and topological materials
inferred← citeshttps://doi.org/10.1177/10943420221107880openalex-snapshot
Enhancing data locality of the conjugate gradient method for high-order matrix-free finite-element implementations
inferred← citeshttps://doi.org/10.1177/10943420231217221openalex-snapshot
Cache-optimized and low-overhead implementations of additive Schwarz methods for high-order FEM multigrid computations
inferred← citeshttps://doi.org/10.2118/194722-msopenalex-snapshot
Application of High Performance Asynchronous Acoustic Wave Equation Stencil Solver into a Land Survey
inferred← citeshttps://doi.org/10.2172/1771077openalex-snapshot
Understanding HPC Benchmark Performance on Intel Broadwell and Cascade Lake Processors
inferred← citeshttps://doi.org/10.32362/2500-316x-2019-7-5-7-19openalex-snapshot
A tool for automatic parallelization of affine programs for systems with shared and distributed memory
inferred← citeshttps://doi.org/10.3997/2214-4609.201903281openalex-snapshot
Alleviating the pressure on memory for seismic modeling
inferred← citeshttps://doi.org/10.48550/arxiv.2103.09235openalex-snapshot
Reducing Redundancy in Data Organization and Arithmetic Calculation for Stencil Computations
inferred← citeshttps://doi.org/10.70675/9a4b7e14za7f4z4a6ezb5f1z795b20080783openalex-snapshot
A combined language and polyhedral approach to heterogeneous parallelism
showing the first 33 of 34 · page through all 34
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.