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Binary Precision Neural Network Manycore Accelerator

https://doi.org/10.1145/3423136
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s42514-019-00014-8openalex-snapshot
ReBNN: in-situ acceleration of binarized neural networks in ReRAM using complementary resistive cell
inferredcites →https://doi.org/10.1109/5.726791openalex-snapshot
Gradient-based learning applied to document recognition
inferredcites →https://doi.org/10.1109/asp-dac47756.2020.9045135openalex-snapshot
NESTA: Hamming Weight Compression-Based Neural Proc. EngineAli Mirzaeian
inferredcites →https://doi.org/10.1109/cvpr.1993.341010openalex-snapshot
Proceedings of IEEE Conference on Computer Vision and Pattern Recognition
inferredcites →https://doi.org/10.1109/cvpr.2016.90openalex-snapshot
Deep Residual Learning for Image Recognition
inferredcites →https://doi.org/10.1109/fccm.2017.46openalex-snapshot
Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA
inferredcites →https://doi.org/10.1109/icassp.2016.7471828openalex-snapshot
FPGA based implementation of deep neural networks using on-chip memory only
inferredcites →https://doi.org/10.1109/ipdpsw.2017.95openalex-snapshot
On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA
inferredcites →https://doi.org/10.1109/iswc.2012.13openalex-snapshot
Introducing a New Benchmarked Dataset for Activity Monitoring
inferredcites →https://doi.org/10.1109/jssc.1974.1050511openalex-snapshot
Design of ion-implanted MOSFET's with very small physical dimensions
inferredcites →https://doi.org/10.1109/jssc.2019.2963616openalex-snapshot
XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks
inferredcites →https://doi.org/10.1109/jstsp.2020.2992384openalex-snapshot
AdaNS: Adaptive Non-Uniform Sampling for Automated Design of Compact DNNs
inferredcites →https://doi.org/10.1109/reconfig48160.2019.8994751openalex-snapshot
TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACs
inferredcites →https://doi.org/10.1109/tcad.2017.2682138openalex-snapshot
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration
inferredcites →https://doi.org/10.1109/tvlsi.2017.2767624openalex-snapshot
An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/tvlsi.2018.2825145openalex-snapshot
Accelerating Convolutional Neural Network With FFT on Embedded Hardware
inferredcites →https://doi.org/10.1145/1465482.1465560openalex-snapshot
Validity of the single processor approach to achieving large scale computing capabilities
inferredcites →https://doi.org/10.1145/2902961.2902986openalex-snapshot
Low-Power Manycore Accelerator for Personalized Biomedical Applications
inferredcites →https://doi.org/10.1145/3005448openalex-snapshot
SPARCNet
inferredcites →https://doi.org/10.1145/3007787.3001163openalex-snapshot
EIE
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3316781.3317739openalex-snapshot
A Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAM
inferredcites →https://doi.org/10.1145/3352460.3358284openalex-snapshot
TensorDIMM
inferredcites →https://doi.org/10.1145/3357526.3357566openalex-snapshot
Inference engine benchmarking across technological platforms from CMOS to RRAM
inferredcites →https://doi.org/10.1145/3358699openalex-snapshot
Heterogeneous Scheduling of Deep Neural Networks for Low-power Real-time Designs
inferredcites →https://doi.org/10.1145/3386263.3407652openalex-snapshot
Energy-Efficient Hardware for Language Guided Reinforcement Learning
inferredcites →https://doi.org/10.1145/3391901openalex-snapshot
EncoDeep
inferredcites →https://doi.org/10.23919/vlsic.2017.8008533openalex-snapshot
BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
inferredcites →https://doi.org/10.3389/fnins.2018.00841openalex-snapshot
Fast Object Tracking on a Many-Core Neural Network Chip
inferredcites →https://doi.org/10.48550/arxiv.1602.02830openalex-snapshot
Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1
inferredcites →https://doi.org/10.48550/arxiv.1711.07128openalex-snapshot
Hello Edge: Keyword Spotting on Microcontrollers
inferredcites →https://doi.org/10.57702/o9raffedopenalex-snapshot
Batch Normalization: Accelerating Deep Network Training by Reducing Internal Covariate Shift

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.future.2026.108486openalex-snapshot
BinDRAM: Binary neural network on unmodified commodity DRAM
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103867openalex-snapshot
GC-BNN: Gain Cell-eDRAM based in-memory Binary Neural Network accelerator
inferred← citeshttps://doi.org/10.1109/ccmcc67628.2025.11380456openalex-snapshot
PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator
inferred← citeshttps://doi.org/10.1109/icra48891.2023.10161258openalex-snapshot
NanoFlowNet: Real-time Dense Optical Flow on a Nano Quadcopter
inferred← citeshttps://doi.org/10.1109/jetcas.2021.3126259openalex-snapshot
Improving Autonomous Nano-Drones Performance via Automated End-to-End Optimization and Deployment of DNNs
inferred← citeshttps://doi.org/10.1109/ojcas.2020.3043737openalex-snapshot
An Energy Efficient EdgeAI Autoencoder Accelerator for Reinforcement Learning
inferred← citeshttps://doi.org/10.1109/tpds.2022.3144614openalex-snapshot
Coordinated Batching and DVFS for DNN Inference on GPU Accelerators
inferred← citeshttps://doi.org/10.1145/3427471openalex-snapshot
A Flexible Multichannel EEG Artifact Identification Processor using Depthwise-Separable Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1145/3623380openalex-snapshot
Reg-Tune: A Regression-Focused Fine-Tuning Approach for Profiling Low Energy Consumption and Latency
inferred← citeshttps://doi.org/10.14569/ijacsa.2023.0141282openalex-snapshot
Research on Efficient CNN Acceleration Through Mixed Precision Quantization: A Comprehensive Methodology
inferred← citeshttps://doi.org/10.2139/ssrn.4883626openalex-snapshot
Enhancing Bnn Storage and Performance Requirements Via Efficient Quantization and Variable Encoding
inferred← citeshttps://doi.org/10.2139/ssrn.6478938openalex-snapshot
TALL BNN: NAND MRAM-based Time-Augmented Last Layer Binary Neural Network Accelerator
inferred← citeshttps://doi.org/10.23919/date56975.2023.10137052openalex-snapshot
Exploiting Kernel Compression on BNNs
inferred← citeshttps://doi.org/10.3389/fhpcp.2026.1853655openalex-snapshot
Enhancing BNN storage and performance requirements via efficient quantization and variable encoding
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