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CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-642-04697-1_37openalex-snapshot
Real-Time Center Detection of an OLED Structure
inferredcites →https://doi.org/10.1109/2.612254openalex-snapshot
Baring it all to software: Raw machines
inferredcites →https://doi.org/10.1109/asap39198.2016openalex-snapshot
2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
inferredcites →https://doi.org/10.1109/aspdac.2007.358040openalex-snapshot
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
inferredcites →https://doi.org/10.1109/fccm.2015.57openalex-snapshot
Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs
inferredcites →https://doi.org/10.1109/fpl38766.2016openalex-snapshot
2016 26th International Conference on Field Programmable Logic and Applications (FPL)
inferredcites →https://doi.org/10.1109/icam.2016.7813532openalex-snapshot
System level power consumption modeling and optimization for coarse-grained reconfigurable architectures
inferredcites →https://doi.org/10.1109/inis.2015.39openalex-snapshot
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array
inferredcites →https://doi.org/10.1109/samos35827.2015openalex-snapshot
2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
inferredcites →https://doi.org/10.1109/sbcci50935.2020.9189899openalex-snapshot
A Machine Learning Approach to Accelerating DSE of Reconfigurable Accelerator Systems
inferredcites →https://doi.org/10.1109/tmm.2006.880562openalex-snapshot
2007 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)
inferredcites →https://doi.org/10.1109/tvlsi.2009.2025280openalex-snapshot
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture
inferredcites →https://doi.org/10.1109/vlsi-soc.2016.7753582openalex-snapshot
A Hybrid Power Estimation Technique to improve IP power models quality
inferredcites →https://doi.org/10.1142/s0129626412500107openalex-snapshot
POLLY — PERFORMING POLYHEDRAL OPTIMIZATIONS ON A LOW-LEVEL INTERMEDIATE REPRESENTATION
inferredcites →https://doi.org/10.1145/1297666.1297669openalex-snapshot
Boosting interpolation with dynamic localized abstraction and redundancy removal
inferredcites →https://doi.org/10.1145/1367045.1367049openalex-snapshot
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
inferredcites →https://doi.org/10.1145/2463209.2488757openalex-snapshot
Polyhedral model based mapping optimization of loop nests for CGRAs
inferredcites →https://doi.org/10.1145/611817.611844openalex-snapshot
Architecture evaluation for power-efficient FPGAs
inferredcites →https://doi.org/10.5555/367072.367839openalex-snapshot
A decade of reconfigurable computing: a visionary retrospective
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-023-05707-0openalex-snapshot
RMSRM: real-time monitoring-based self-reconfiguration mechanism in reconfigurable PE array
inferred← citeshttps://doi.org/10.1109/asap71856.2026.00025openalex-snapshot
Symbolic Energy Analysis for Nested Loop Accelerators
inferred← citeshttps://doi.org/10.1109/clusterworkshops61563.2024.00041openalex-snapshot
Post-Route Power Estimation: A Case Study of RIKEN-CGRA
inferred← citeshttps://doi.org/10.1109/sbesc68008.2025.11288812openalex-snapshot
A Simulation Methodology for Transparent Coarse-Grained Reconfigurable Architectures
inferred← citeshttps://doi.org/10.1109/tcad.2024.3383349openalex-snapshot
GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient Processing at the Edge
inferred← citeshttps://doi.org/10.1145/3656642openalex-snapshot
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA
inferred← citeshttps://doi.org/10.1145/3706594.3726977openalex-snapshot
A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
inferred← citeshttps://doi.org/10.1145/3723045openalex-snapshot
PRISA: A Potential Region-based Intelligent Search Algorithm for Dataflow Graph Mapping in Spatial CGRAs
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3855958/v1openalex-snapshot
WITHDRAWN: CGRA Implementation of HEVC Decoder Using Predictable Context Directed Pattern Matching With Efficient and Flexible Memory Architecture
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3855958/v2openalex-snapshot
WITHDRAWN: CGRA Implementation of HEVC Decoder Using Predictable Context Directed Pattern Matching With Efficient and Flexible Memory Architecture
inferred← citeshttps://doi.org/10.3389/fhpcp.2025.1572844openalex-snapshot
FPGA innovation research in the Netherlands: present landscape and future outlook
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