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A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/cvpr.2016.308openalex-snapshot
Rethinking the Inception Architecture for Computer Vision
inferredcites →https://doi.org/10.1109/cvpr.2016.90openalex-snapshot
Deep Residual Learning for Image Recognition
inferredcites →https://doi.org/10.1109/dac18072.2020.9218652openalex-snapshot
AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC
inferredcites →https://doi.org/10.1109/fccm.2012.25openalex-snapshot
ZUMA: An Open FPGA Overlay Architecture
inferredcites →https://doi.org/10.1109/fccm.2014.12openalex-snapshot
A Fully Pipelined and Dynamically Composable Architecture of CGRA
inferredcites →https://doi.org/10.1109/fccm.2019.00035openalex-snapshot
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs
inferredcites →https://doi.org/10.1109/fpl.2018.00024openalex-snapshot
FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs
inferredcites →https://doi.org/10.1109/fpl.2018.00031openalex-snapshot
A Survey on FPGA Virtualization
inferredcites →https://doi.org/10.1109/fpl.2018.00077openalex-snapshot
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration
inferredcites →https://doi.org/10.1109/fpt.2014.7082811openalex-snapshot
Online scheduling for FPGA computation in the Cloud
inferredcites →https://doi.org/10.1109/hpca47549.2020.00027openalex-snapshot
PREMA: A Predictive Multi-Task Scheduling Algorithm For Preemptible Neural Processing Units
inferredcites →https://doi.org/10.1109/isca45697.2020.00084openalex-snapshot
DeepRecSys: A System for Optimizing End-To-End At-Scale Neural Recommendation Inference
inferredcites →https://doi.org/10.1109/iscas30516.2016openalex-snapshot
2016 IEEE International Symposium on Circuits and Systems (ISCAS)
inferredcites →https://doi.org/10.1109/mm.2020.2974843openalex-snapshot
MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance
inferredcites →https://doi.org/10.1109/rtas.2019.00011openalex-snapshot
Fractional GPUs: Software-Based Compute and Memory Bandwidth Reservation for GPUs
inferredcites →https://doi.org/10.1109/rtss46320.2019.00037openalex-snapshot
MCS-IOV: Real-Time I/O Virtualization for Mixed-Criticality Systems
inferredcites →https://doi.org/10.1109/tcad.2017.2705069openalex-snapshot
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA
inferredcites →https://doi.org/10.1109/tcad.2019.2930577openalex-snapshot
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators
inferredcites →https://doi.org/10.1145/2678373.2665678openalex-snapshot
A reconfigurable fabric for accelerating large-scale datacenter services
inferredcites →https://doi.org/10.1145/3020078.3021738openalex-snapshot
An OpenCL™ Deep Learning Accelerator on Arria 10
inferredcites →https://doi.org/10.1145/3289185openalex-snapshot
[DL] A Survey of FPGA-based Neural Network Inference Accelerators
inferredcites →https://doi.org/10.1145/3603165.3607390openalex-snapshot
Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/aihcir67580.2025.11405112openalex-snapshot
Multi-sensor Integrated Information Processing System Based on Dynamic Partition of FPGA
inferred← citeshttps://doi.org/10.1109/aihcir67580.2025.11405417openalex-snapshot
Design of Multi-sensor Signal Processing Algorithm Based on FPGA Common Operator Library
inferred← citeshttps://doi.org/10.1109/mcsoc67473.2025.00108openalex-snapshot
Instruction-Based Coordination of Heterogeneous Processing Units for Acceleration of DNN Inference
inferred← citeshttps://doi.org/10.1109/mpcon66082.2025.11256642openalex-snapshot
Performance and Power Analysis of feed-forward Artificial Neural Network In Xilinx’s 7 Series Field Programmable Gate Array
inferred← citeshttps://doi.org/10.1109/mpcon66082.2025.11256732openalex-snapshot
Performance and Power Analysis of feed-forward Artificial Neural Network In Xilinx’s 7 Series Field Programmable Gate Array
inferred← citeshttps://doi.org/10.1109/tc.2022.3214113openalex-snapshot
Serving Multi-DNN Workloads on FPGAs: A Coordinated Architecture, Scheduling, and Mapping Perspective
inferred← citeshttps://doi.org/10.1109/tpds.2023.3276759openalex-snapshot
CD-MSA: Cooperative and Deadline-Aware Scheduling for Efficient Multi-Tenancy on DNN Accelerators
inferred← citeshttps://doi.org/10.1145/3579371.3589095openalex-snapshot
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization
inferred← citeshttps://doi.org/10.31219/osf.io/fk3r7openalex-snapshot
Complexities for the Indian Economy of China's Growing Technological Competence
inferred← citeshttps://doi.org/10.31237/osf.io/4yr8jopenalex-snapshot
Leveraging Artificial Intelligence in the Cyber Workplace: Prospects and Limitations for the Cyber Economy
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