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[DL] A Survey of FPGA-based Neural Network Inference Accelerators
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s11263-015-0816-yopenalex-snapshot
ImageNet Large Scale Visual Recognition Challenge
inferredcites →https://doi.org/10.1109/asap.2017.7995253openalex-snapshot
Fast and efficient implementation of Convolutional Neural Networks on FPGA
inferredcites →https://doi.org/10.1109/aspdac.2016.7428073openalex-snapshot
Design space exploration of FPGA-based Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/aspdac.2017.7858394openalex-snapshot
FPGA-based accelerator for long short-term memory recurrent neural networks
inferredcites →https://doi.org/10.1109/cvpr.1993openalex-snapshot
Proceedings of IEEE Conference on Computer Vision and Pattern Recognition
inferredcites →https://doi.org/10.1109/cvpr.2014.81openalex-snapshot
Rich Feature Hierarchies for Accurate Object Detection and Semantic Segmentation
inferredcites →https://doi.org/10.1109/cvpr.2015.7298594openalex-snapshot
Going deeper with convolutions
inferredcites →https://doi.org/10.1109/cvpr.2015.7298809openalex-snapshot
Efficient and accurate approximations of nonlinear convolutional networks
inferredcites →https://doi.org/10.1109/cvpr.2016.90openalex-snapshot
Deep Residual Learning for Image Recognition
inferredcites →https://doi.org/10.1109/cvpr.2019.00293openalex-snapshot
MnasNet: Platform-Aware Neural Architecture Search for Mobile
inferredcites →https://doi.org/10.1109/fccm.2017.13openalex-snapshot
Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA
inferredcites →https://doi.org/10.1109/fccm.2017.25openalex-snapshot
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates
inferredcites →https://doi.org/10.1109/fccm.2017.43openalex-snapshot
Customizing Neural Networks for Efficient FPGA Implementation
inferredcites →https://doi.org/10.1109/fccm.2017.47openalex-snapshot
Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer
inferredcites →https://doi.org/10.1109/fccm.2017.62openalex-snapshot
Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms
inferredcites →https://doi.org/10.1109/fccm.2017.64openalex-snapshot
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1109/fccm.2018.00018openalex-snapshot
ReBNet: Residual Binarized Neural Network
inferredcites →https://doi.org/10.1109/fpl.2016.7577315openalex-snapshot
Overcoming resource underutilization in spatial CNN accelerators
inferredcites →https://doi.org/10.1109/fpl.2018.00035openalex-snapshot
Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA
inferredcites →https://doi.org/10.1109/fpt.2016.7929192openalex-snapshot
Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC
inferredcites →https://doi.org/10.1109/fpt.2016.7929549openalex-snapshot
Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/fpt.2017.8280147openalex-snapshot
Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA
inferredcites →https://doi.org/10.1109/tcad.2017.2705069openalex-snapshot
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA
inferredcites →https://doi.org/10.1137/1.9781611970364openalex-snapshot
Arithmetic Complexity of Computations
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2847263.2847265openalex-snapshot
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/2847263.2847276openalex-snapshot
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2934583.2934644openalex-snapshot
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
inferredcites →https://doi.org/10.1145/3020078.3021698openalex-snapshot
Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/3020078.3021727openalex-snapshot
Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System
inferredcites →https://doi.org/10.1145/3020078.3021736openalex-snapshot
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/3020078.3021738openalex-snapshot
An OpenCL™ Deep Learning Accelerator on Arria 10
inferredcites →https://doi.org/10.1145/3020078.3021741openalex-snapshot
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs
inferredcites →https://doi.org/10.1145/3020078.3021782openalex-snapshot
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only)
inferredcites →https://doi.org/10.1145/3020078.3021786openalex-snapshot
A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only)
inferredcites →https://doi.org/10.1145/3061639.3062207openalex-snapshot
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
inferredcites →https://doi.org/10.1145/3061639.3062244openalex-snapshot
Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1145/3065386openalex-snapshot
ImageNet classification with deep convolutional neural networks
inferredcites →https://doi.org/10.1145/3174243.3174257openalex-snapshot
Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA
inferredcites →https://doi.org/10.1145/3186332openalex-snapshot
Toolflows for Mapping Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1145/3194554.3194597openalex-snapshot
Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs
inferredcites →https://doi.org/10.1145/3218603.3218615openalex-snapshot
A Fully Onchip Binarized Convolutional Neural Network FPGA Impelmentation with Accurate Inference
inferredcites →https://doi.org/10.23919/fpl.2017.8056771openalex-snapshot
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA
inferredcites →https://doi.org/10.23919/fpl.2017.8056794openalex-snapshot
A high-throughput reconfigurable processing array for neural networks
inferredcites →https://doi.org/10.23919/fpl.2017.8056820openalex-snapshot
Accelerating low bit-width convolutional neural networks with embedded FPGA
inferredcites →https://doi.org/10.23919/fpl.2017.8056824openalex-snapshot
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks
inferredcites →https://doi.org/10.23919/fpl.2017.8056850openalex-snapshot
Scalable high-performance architecture for convolutional ternary neural networks on FPGA
inferredcites →https://doi.org/10.48550/arxiv.1409.1556openalex-snapshot
Very Deep Convolutional Networks for Large-Scale Image Recognition
inferredcites →https://doi.org/10.48550/arxiv.1512.02595openalex-snapshot
Deep Speech 2: End-to-End Speech Recognition in English and Mandarin
inferredcites →https://doi.org/10.48550/arxiv.1602.07360openalex-snapshot
SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size
inferredcites →https://doi.org/10.48550/arxiv.1606.06160openalex-snapshot
DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients
inferredcites →https://doi.org/10.48550/arxiv.1612.01064openalex-snapshot
Trained Ternary Quantization
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A Marr's Three‐Level Analytical Framework for Neuromorphic Electronic Systems
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Evaluating and analyzing the energy efficiency of CNN inference on high‐performance GPU
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Deep reinforcement learning‐based autonomous parking design with neural network compute accelerators
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LUT‐DSP usage trade‐off for re‐configurable convolution acceleration core based on small logarithmic floating point representation
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A design of EEGNet‐based inference processor for pattern recognition of EEG using FPGA
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Misbehavior Detection With Collective Perception in V2X Networks: A Survey
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High-Throughput Machine Learning Approaches for Network Attacks Detection on FPGA
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XDN: Towards Efficient Inference of Residual Neural Networks on Cambricon Chips
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Space Use-Case: Onboard Satellite Image Classification
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Hardware/Software Co-design for Convolutional Neural Networks Acceleration: A Survey and Open Issues
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Scalable and Energy-Efficient Deep Learning for Distributed AIoT Applications Using Modular Cognitive IoT Hardware
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Compilation and Optimizations for Efficient Machine Learning on Embedded Systems
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ONNX-To-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
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Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA
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Coarse-Grained Reconfigurable Arrays for High-Performance Low-Power Deep Neural Networks on Embedded Devices
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Machine Learning Systems for High Performance and Dependability: The FPGA Roleplay
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An Anatomization of FPGA-Based Neural Networks
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Reconfigurable Architectures: The Shift from General Systems to Domain Specific Solutions
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Hardware and Software Co-optimization of Convolutional and Self-attention Combined Model Based on FPGA
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A Review of Deep Learning Techniques of Chest X-ray Analysis for Thoracic Disorders
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Resource-constrained FPGA/DNN co-design
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Optimized convolutional neural network architectures for efficient on-device vision-based object detection
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Computational intelligence enabled hardware software co design for energy efficient Edge Artificial Intelligence
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Analysis and codesign of electronic–photonic integrated circuit hardware accelerator for machine learning application
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Towards An FPGA-targeted Hardware/Software Co-design Framework for CNN-based Edge Computing
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A systematic literature review on hardware implementation of artificial intelligence algorithms
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Learning-assisted schedulability analysis: opportunities and limitations
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An Automated Design Flow for Adaptive Neural Network Hardware Accelerators
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A dedicated hardware accelerator for real-time acceleration of YOLOv2
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Automated CNN back-propagation pipeline generation for FPGA online training
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Post-configuration Activation of Hardware Trojans in FPGAs
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Achieving energy efficiency in FPGA-based neural network inference accelerators through approximate computing
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Personal health guardian - Product series
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FPGA based neural network accelerators
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FPGA implementation of an optimized neural network for CFD acceleration
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High-efficiency low-power microdefect detection in photovoltaic cells via a field programmable gate array-accelerated dual-flow network
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FPGA technology in healthcare: A comprehensive review of hardware and software solutions for diagnostics, imaging, and patient care
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A pipelined CNN accelerator for SSD object detection on multi-FPGA
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TileNET: Hardware accelerator for ternary Convolutional Neural Networks
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Characterization of Execution Time Variability in FPGA-Based AI-Accelerators
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Using hls4ml to Map Convolutional Neural Networks on Interconnected FPGA Devices
inferred← citeshttps://doi.org/10.1109/fccm68464.2026.00018openalex-snapshot
FHPSAC: FPGA-based High-Parallelism SAC Accelerator
inferred← citeshttps://doi.org/10.1109/fccm68464.2026.00041openalex-snapshot
ImageHD: Energy-Efficient On-Device Continual Learning of Visual Representations via Hyperdimensional Computing
inferred← citeshttps://doi.org/10.1109/fpl.2019.00043openalex-snapshot
Network Intrusion Detection Using Neural Networks on FPGA SoCs
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00050openalex-snapshot
A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00058openalex-snapshot
Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler Stack
inferred← citeshttps://doi.org/10.1109/fpl60245.2023.00039openalex-snapshot
Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks
inferred← citeshttps://doi.org/10.1109/gcaiot51063.2020.9345903openalex-snapshot
Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs
inferred← citeshttps://doi.org/10.1109/hpec43674.2020.9286149openalex-snapshot
Survey of Machine Learning Accelerators
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643536openalex-snapshot
A Hybrid FPGA-ASIC Delayed Feedback Reservoir System to Enable Spectrum Sensing/Sharing for Low Power IoT Devices ICCAD Special Session Paper
inferred← citeshttps://doi.org/10.1109/iccad69956.2026.11643090openalex-snapshot
Optimizing CNN-to-FPGA Conversion with hls4ml: Resource, Latency, and Accuracy Trade-offs for Fashion-MNIST Classification
inferred← citeshttps://doi.org/10.1109/icce63647.2025.10930191openalex-snapshot
A Winograd-Convolution-Based Accelerator on FPGA for Real-Time Object Detection with Effective On-Chip Buffer Access Patterns
inferred← citeshttps://doi.org/10.1109/iccebs58601.2023.10449153openalex-snapshot
Acceleration Techniques for Video-Based Self-Recuperation Training – State-of-the-Art Review
inferred← citeshttps://doi.org/10.1109/iccmc69250.2026.11625074openalex-snapshot
Design of Energy-Efficient TinyML Accelerators: From MATLAB Modeling to FPGA and Embedded Deployment
inferred← citeshttps://doi.org/10.1109/icct56141.2022.10072633openalex-snapshot
Reconfigurable Multi-algorithm Neural Network Accelerator Based on Target Detection
inferred← citeshttps://doi.org/10.1109/icei65890.2026.11447502openalex-snapshot
Machine Learning Approaches for Intelligent Reflecting Surface-Assisted MIMO Communication Systems: A Survey
inferred← citeshttps://doi.org/10.1109/icfpt51103.2020.00018openalex-snapshot
INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUs
inferred← citeshttps://doi.org/10.1109/icfpt64416.2024.11113430openalex-snapshot
Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
inferred← citeshttps://doi.org/10.1109/icist52614.2021.9440554openalex-snapshot
FPGA Implementation of Object Detection Accelerator Based on Vitis-AI
inferred← citeshttps://doi.org/10.1109/icmlas67792.2026.11483930openalex-snapshot
Energy-Efficient Fpga Acceleration for Distributed Machine Learning Inference in Cloud-Scale E-Commerce Systems
inferred← citeshttps://doi.org/10.1109/icmre54455.2022.9734102openalex-snapshot
Open-Source Educational Platform for FPGA Accelerated AI in Robotics
inferred← citeshttps://doi.org/10.1109/iecon55916.2024.10905351openalex-snapshot
Benchmarking Performance of Neural Network Architectures in Conventional Industrial Hardware
inferred← citeshttps://doi.org/10.1109/infocomwkshps61880.2024.10620877openalex-snapshot
Hardware Acceleration for Real-Time Wildfire Detection Onboard Drone Networks
inferred← citeshttps://doi.org/10.1109/iolts69666.2026.11633646openalex-snapshot
Hardware-Aware Runtime Detection of Soft-Error Anomalies in DPU-Accelerated Neural Networks
inferred← citeshttps://doi.org/10.1109/ipdpsw50202.2020.00034openalex-snapshot
Optimizing OpenCL Kernels and Runtime for DNN Inference on FPGAs
inferred← citeshttps://doi.org/10.1109/ipdpsw55747.2022.00027openalex-snapshot
On How to Push Efficient Medical Semantic Segmentation to the Edge: the SENECA approach
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401166openalex-snapshot
SoWaF: Shuffling of Weights and Feature Maps: A Novel Hardware Intrinsic Attack (HIA) on Convolutional Neural Network (CNN)
inferred← citeshttps://doi.org/10.1109/iscas66217.2026.11562547openalex-snapshot
ViMA: A Decoupled FPGA Accelerator for Vision Mamba with Resource-Space Exploration
inferred← citeshttps://doi.org/10.1109/isocc50952.2020.9332958openalex-snapshot
Mixture of Deterministic and Stochastic Quantization Schemes for Lightweight CNN
inferred← citeshttps://doi.org/10.1109/ispass57527.2023.00024openalex-snapshot
CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (TinyML) Acceleration on FPGAs
inferred← citeshttps://doi.org/10.1109/isqed57927.2023.10129353openalex-snapshot
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators
inferred← citeshttps://doi.org/10.1109/isqed60706.2024.10528372openalex-snapshot
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00099openalex-snapshot
Accelerating Compact Convolutional Neural Networks with Multi-threaded Data Streaming
inferred← citeshttps://doi.org/10.1109/itc-cscc52171.2021.9501454openalex-snapshot
MNN: A Solution to Implement Neural Networks into a Memory-based Reconfigurable Logic Device (MRLD)
inferred← citeshttps://doi.org/10.1109/itc-cscc62988.2024.10628398openalex-snapshot
Deep-BMNN: Implementing Sparse Binary Neural Networks in Memory-Based Reconfigurable Processor (MRP)
inferred← citeshttps://doi.org/10.1109/jbhi.2023.3296142openalex-snapshot
NERONE: The Fast Way to Efficiently Execute Your Deep Learning Algorithm at the Edge
inferred← citeshttps://doi.org/10.1109/jetcas.2020.3014503openalex-snapshot
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators
inferred← citeshttps://doi.org/10.1109/jproc.2025.3623023openalex-snapshot
Field-Programmable Gate Array Architecture for Deep Learning: Survey and Future Directions
inferred← citeshttps://doi.org/10.1109/jssc.2026.3669626openalex-snapshot
A 13.8% Speed-Enhanced 1 T Mask ROM by Algorithmically Signed Program Data on 3-nm Fin-FET Logic CMOS
inferred← citeshttps://doi.org/10.1109/lars/sbr/wre59448.2023.10333052openalex-snapshot
FPGA-based Accelerator for Convolutional Neural Network Application in Mobile Robotics
inferred← citeshttps://doi.org/10.1109/lca.2022.3227643openalex-snapshot
Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures
inferred← citeshttps://doi.org/10.1109/les.2020.3017455openalex-snapshot
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators
inferred← citeshttps://doi.org/10.1109/les.2024.3446896openalex-snapshot
Characterizing CNN Throughput and Energy Under Multithreaded and Multiaccelerator Execution
inferred← citeshttps://doi.org/10.1109/mcas.2021.3071609openalex-snapshot
A Survey of FPGA-Based Robotic Computing
inferred← citeshttps://doi.org/10.1109/mcsoc60832.2023.00047openalex-snapshot
A Near-Memory Dynamically Programmable Many-Core Overlay
inferred← citeshttps://doi.org/10.1109/mipro70003.2026.11591835openalex-snapshot
Application of FPGA-Based AI Systems for Smart Agriculture: A Review Across Field Crops, Fruits, and Vegetables
inferred← citeshttps://doi.org/10.1109/mnet.211.2100302openalex-snapshot
Edge Intelligence for Smart Metro Systems: Architecture and Enabling Technologies
inferred← citeshttps://doi.org/10.1109/ojia.2026.3671845openalex-snapshot
FPGA-Enabled Deep Learning for Real-Time DC Series Arc Fault Detection
inferred← citeshttps://doi.org/10.1109/prime55000.2022.9816841openalex-snapshot
Profiling of CNNs using the MATLAB FPGA-based Deep Learning Processor
inferred← citeshttps://doi.org/10.1109/recosoc48741.2019.9034972openalex-snapshot
The AV says: Your Hardware Definitions Were Updated!
inferred← citeshttps://doi.org/10.1109/saci60582.2024.10619919openalex-snapshot
Evaluation of DarkNet19 and DarkNet53 Inference Time on CPU, GPU, and FPGA
inferred← citeshttps://doi.org/10.1109/scw63240.2024.00074openalex-snapshot
ProTEA: Programmable Transformer Encoder Acceleration on FPGA
inferred← citeshttps://doi.org/10.1109/sitis61268.2023.00080openalex-snapshot
Embedded Artificial Intelligence, Impact of a Fast Learning Architecture on OFDM Receiver Performances
inferred← citeshttps://doi.org/10.1109/taslp.2021.3051331openalex-snapshot
Evolving Multi-Resolution Pooling CNN for Monaural Singing Voice Separation
inferred← citeshttps://doi.org/10.1109/tbcas.2019.2956435openalex-snapshot
Who is the Winner? Memristive-CMOS Hybrid Modules: CNN-LSTM Versus HTM
inferred← citeshttps://doi.org/10.1109/tbcas.2020.3036081openalex-snapshot
Hardware Implementation of Deep Network Accelerators Towards Healthcare and Biomedical Applications
inferred← citeshttps://doi.org/10.1109/tbcas.2022.3161133openalex-snapshot
Data-Driven Real-Time Magnetic Tracking Applied to Myokinetic Interfaces
inferred← citeshttps://doi.org/10.1109/tc.2020.3033730openalex-snapshot
Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs
inferred← citeshttps://doi.org/10.1109/tc.2022.3211430openalex-snapshot
End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators
inferred← citeshttps://doi.org/10.1109/tc.2022.3214117openalex-snapshot
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs
inferred← citeshttps://doi.org/10.1109/tc.2023.3334140openalex-snapshot
Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators
inferred← citeshttps://doi.org/10.1109/tc.2025.3525606openalex-snapshot
Karatsuba Matrix Multiplication and Its Efficient Custom Hardware Implementations
inferred← citeshttps://doi.org/10.1109/tcad.2021.3072340openalex-snapshot
INCAME: Interruptible CNN Accelerator for Multirobot Exploration
inferred← citeshttps://doi.org/10.1109/tcad.2025.3591734openalex-snapshot
FPGA-Friendly Architecture of Processing Elements for Efficient and Accurate Quantized CNNs
inferred← citeshttps://doi.org/10.1109/tcad.2026.3663250openalex-snapshot
SASRO: Hardware--Software Codesign of Real-Time Self-Adaptive Deep Stereo Toward Robotic Applications
inferred← citeshttps://doi.org/10.1109/tcasai.2025.3604383openalex-snapshot
HiTEA-3D: A Design Framework for High-Throughput and Energy-Aware 3D CNN Acceleration on FPGA
inferred← citeshttps://doi.org/10.1109/tcsii.2022.3148228openalex-snapshot
An Area-Efficient FPGA Implementation of a Real-Time Multi-Class Classifier for Binary Images
inferred← citeshttps://doi.org/10.1109/tcsii.2022.3179229openalex-snapshot
Algorithm/Accelerator Co-Design and Co-Search for Edge AI
inferred← citeshttps://doi.org/10.1109/tcss.2021.3059318openalex-snapshot
Collaborative Edge Computing With FPGA-Based CNN Accelerators for Energy-Efficient and Time-Aware Face Tracking System
inferred← citeshttps://doi.org/10.1109/tetci.2025.3551934openalex-snapshot
Reconfigurable Digital FPGA Implementations for Neuromorphic Computing: A Survey on Recent Advances and Future Directions
inferred← citeshttps://doi.org/10.1109/tmm.2021.3134158openalex-snapshot
A Generalized Zero-Shot Quantization of Deep Convolutional Neural Networks Via Learned Weights Statistics
inferred← citeshttps://doi.org/10.1109/tpds.2021.3129615openalex-snapshot
Elastic Significant Bit Quantization and Acceleration for Deep Neural Networks
inferred← citeshttps://doi.org/10.1109/tpds.2025.3555968openalex-snapshot
WCET Estimation for CNN Inference on FPGA SoC With Multi-DPU Engines
inferred← citeshttps://doi.org/10.1109/tpds.2026.3667207openalex-snapshot
Adaptive Block-Wise Mapping With Intra-Block Resource Allocation for Multi-DNN Workloads on Heterogeneous Accelerator Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2020.3046075openalex-snapshot
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3305937openalex-snapshot
Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary Systolic Architecture
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3530785openalex-snapshot
Strassen Multisystolic Array Hardware Architectures
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3554880openalex-snapshot
Real-Time Driver Monitoring: Implementing FPGA-Accelerated CNNs for Pose Detection
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3716149openalex-snapshot
HEADS: Accuracy--Makespan Co-Optimization for Multitenant Multi-FPGA Edge Systems
inferred← citeshttps://doi.org/10.1109/vdat72243.2026.11704615openalex-snapshot
Edge AI Wildlife Classification with FPGA-Based Deterministic Deterrence on PYNQ-Z2
inferred← citeshttps://doi.org/10.1109/vlsi-dat54769.2022.9768052openalex-snapshot
An Embedded CNN Design for Edge Devices Based on Logarithmic Computing
inferred← citeshttps://doi.org/10.1126/sciadv.adk1525openalex-snapshot
Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines
inferred← citeshttps://doi.org/10.1145/3309551openalex-snapshot
Deep Neural Network Approximation for Custom Hardware
inferred← citeshttps://doi.org/10.1145/3362743.3362964openalex-snapshot
Embedded Deep Inference in Practice
inferred← citeshttps://doi.org/10.1145/3460288openalex-snapshot
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture
inferred← citeshttps://doi.org/10.1145/3461478openalex-snapshot
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components
inferred← citeshttps://doi.org/10.1145/3467476openalex-snapshot
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization
inferred← citeshttps://doi.org/10.1145/3472770openalex-snapshot
Reconfigurable Framework for Resilient Semantic Segmentation for Space Applications
inferred← citeshttps://doi.org/10.1145/3480170openalex-snapshot
A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud
inferred← citeshttps://doi.org/10.1145/3546182openalex-snapshot
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units
inferred← citeshttps://doi.org/10.1145/3549536openalex-snapshot
Data and Computation Reuse in CNNs Using Memristor TCAMs
inferred← citeshttps://doi.org/10.1145/3549937openalex-snapshot
Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array
inferred← citeshttps://doi.org/10.1145/3594540openalex-snapshot
Automatic Generation of Resource and Accuracy Configurable Processing Elements
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