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Proceedings of the 59th ACM/IEEE Design Automation Conference

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Generalized zero-shot learning for classifying unseen wafer map patterns
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Modeling and physical attack resistant authentication protocol with double PUFs
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RRAM serial configuration for the generation of random bits
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Machine learning attacks resistant strong PUF design utilizing response obfuscates challenge with lower hardware overhead
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Symbolic-functional representation inference for gate-level power estimation
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FourierPIM: High-throughput in-memory Fast Fourier Transform and polynomial multiplication
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Design and implementation of a synchronous Hardware Performance Monitor for a RISC-V space-oriented processor
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Distributed Analytics For Big Data: A Survey
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A temporally coded multilayer spiking neural network and its memristor-based hardware implementation
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SynapseHD: A unified training framework for bridging spiking neural networks and hyperdimensional computing
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Raw event-based adversarial attacks for Spiking Neural Networks with configurable latencies
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On density and dentability in Hilbert spaces
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VIDGCN: Embracing input data diversity with a configurable graph convolutional network accelerator
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FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach
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Using MAST for modeling and response-time analysis of real-time applications with GPUs
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Efficient maximum reaction time analysis for data chains of real-time tasks in multiprocessor systems
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Reinforcement learning in integrated circuits: Design, synthesis, layout, and hardware security
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Gate-level voltage scaling for low-power design using multiple supply voltages
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Technology mapping algorithm for heterogeneous field programmable gate arrays
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Quantum State Preparation with Optimal Circuit Depth: Implementations and Applications
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Experimental Equivalence Checking of Quantum Circuits by Nonlocality
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LCID: LLM-powered Cognitive Impairment Diagnosis over Long-term Multimodal Sensor Data with Hyperdimensional Encoding and Attentional Fusion
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Planning Point Directed Exploring Tree Routing Algorithm
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Open-source differentiable lithography imaging framework
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Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
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Low-power gated and buffered clock network construction
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High-Level Test Synthesis
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Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System
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A Solicitous Approach to Smart Contract Verification
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SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V
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DF-GAS: a Distributed FPGA-as-a-Service Architecture towards Billion-Scale Graph-based Approximate Nearest Neighbor Search
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SUPPORTING ENERGY-BASED LEARNING WITH AN ISING MACHINE SUBSTRATE: A CASE STUDY ON RBM
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RACE: An Efficient Redundancy-aware Accelerator for Dynamic Graph Neural Network
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A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures
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TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor Computing
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Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms
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FMCC: Flexible Measurement-based Quantum Computation over Cluster State
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Secure and Lightweight Authentication Protocol Using PUF for the IoT-based Wireless Sensor Network
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Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems
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A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices
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IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications
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LightZone: Lightweight Hardware-Assisted In-Process Isolation for ARM64
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Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference
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Dynamic Co-Optimization Compiler: Leveraging Multi-Agent Reinforcement Learning for Enhanced DNN Accelerator Performance
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inferred← citeshttps://doi.org/10.1145/3658617.3697585openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3658617.3697594openalex-snapshot
DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations
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inferred← citeshttps://doi.org/10.1145/3658617.3697722openalex-snapshot
Area-Oriented Optimization After Standard-Cell Mapping
inferred← citeshttps://doi.org/10.1145/3658617.3697753openalex-snapshot
Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural Networks
inferred← citeshttps://doi.org/10.1145/3658617.3697788openalex-snapshot
Deploying Diffusion Models with Scheduling Space Search and Memory Overflow Prevention Based on Graph Optimization
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Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and Reliability
inferred← citeshttps://doi.org/10.1145/3669940.3707254openalex-snapshot
Early Termination for Hyperdimensional Computing Using Inferential Statistics
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Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures
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Barber: Balancing Thermal Relaxation Deviations of NISQ Programs by Exploiting Bit-Inverted Circuits
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DeepGate3: Towards Scalable Circuit Representation Learning
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BQSim: GPU-accelerated Batch Quantum Circuit Simulation using Decision Diagram
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An Efficient ReRAM-based Accelerator for Asynchronous Iterative Graph Processing
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inferred← citeshttps://doi.org/10.1145/3702005openalex-snapshot
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Steered Bubble: An Interposer-based Deadlock Recovery Algorithm for Multi-chiplet Systems
inferred← citeshttps://doi.org/10.1145/3716505openalex-snapshot
Validation of CHC Satisfiability with ATHENA
inferred← citeshttps://doi.org/10.1145/3719654openalex-snapshot
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Interactive Visual Performance Space Exploration of Operational Amplifiers with Differentiable Neural Network Surrogate Models
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Accelerating Verifiable Queries over Blockchain Database System Using Processing-in-memory
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RedPIM: An Efficient PIM Accelerator Design with Reduced Analog-to-Digital Conversions
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Towards Floating Point-Based AI Acceleration: Hybrid PIM with Non-Uniform Data Format and Reduced Multiplications
inferred← citeshttps://doi.org/10.1145/3769307openalex-snapshot
Holistic Optimization Framework for FPGA Accelerators
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ISRLUT: Integer-Only FHD Image Super-Resolution Based on Neural Lookup Table and Near-Memory Computing
inferred← citeshttps://doi.org/10.1145/3771288openalex-snapshot
CD-LLM: A Heterogeneous Multi-FPGA System for Batched Decoding of 70B+ LLMs Using a Compute-Dedicated Architecture
inferred← citeshttps://doi.org/10.1145/3772277openalex-snapshot
Deep Learning on RISC-V Platforms at the Edge: A Perspective on the Hardware and Software Support
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Exploring Trade-Offs in Spiking Neural Networks
inferred← citeshttps://doi.org/10.1177/003754979306000202openalex-snapshot
Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits
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Parameter-based Engineering Changes for a Distributed Engineering Environment
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Force-directed algorithms for schematic drawings and placement: A survey
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A holistic cyber-physical security protocol for authenticating the provenance and integrity of structural health monitoring imagery data
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Formal architectural models for agent-based service systems
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A Client Selection Method Based on Loss Function Optimization for Federated Learning
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