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SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V

https://doi.org/10.1145/3566053
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-319-62105-0_11openalex-snapshot
KASLR is Dead: Long Live KASLR
inferredcites →https://doi.org/10.1007/s11432-016-9030-0openalex-snapshot
Attacking OpenSSL ECDSA with a small amount of side-channel information
inferredcites →https://doi.org/10.1007/s11432-018-9678-8openalex-snapshot
On-demand cut off the covert channel to mitigate meltdown
inferredcites →https://doi.org/10.1016/j.comnet.2005.01.010openalex-snapshot
Remote timing attacks are practical
inferredcites →https://doi.org/10.1109/micro.2005.3openalex-snapshot
Proceedings. 38th Annual IEEE/ACM International Symposium on Microarchitecture
inferredcites →https://doi.org/10.1145/1024393.1024404openalex-snapshot
Secure program execution via dynamic information flow tracking
inferredcites →https://doi.org/10.1145/1037187.1024404openalex-snapshot
Secure program execution via dynamic information flow tracking
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1273440.1250722openalex-snapshot
Raksha
inferredcites →https://doi.org/10.1145/1394608.1382153openalex-snapshot
Flexible Hardware Acceleration for Instruction-Grain Program Monitoring
inferredcites →https://doi.org/10.1145/1456508.1456514openalex-snapshot
Deconstructing new cache designs for thwarting software cache-based side channel attacks
inferredcites →https://doi.org/10.1145/2228360openalex-snapshot
Proceedings of the 49th Annual Design Automation Conference
inferredcites →https://doi.org/10.1145/2487726openalex-snapshot
Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy
inferredcites →https://doi.org/10.1145/3079856.3080223openalex-snapshot
EDDIE
inferredcites →https://doi.org/10.1145/3243176openalex-snapshot
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques
inferredcites →https://doi.org/10.1145/3316781openalex-snapshot
Proceedings of the 56th Annual Design Automation Conference 2019
inferredcites →https://doi.org/10.1145/3352460openalex-snapshot
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
inferredcites →https://doi.org/10.1145/3352460.3358306openalex-snapshot
NDA
inferredcites →https://doi.org/10.1145/3352460.3358310openalex-snapshot
MI6
inferredcites →https://doi.org/10.1145/3352460.3358314openalex-snapshot
CleanupSpec
inferredcites →https://doi.org/10.1145/3411504.3421216openalex-snapshot
SpectreRewind
inferredcites →https://doi.org/10.1145/3442479openalex-snapshot
Survey of Transient Execution Attacks and Their Mitigations
inferredcites →https://doi.org/10.1145/3445814.3446708openalex-snapshot
Speculative interference attacks: breaking invisible speculation schemes
inferredcites →https://doi.org/10.1145/3466752.3480068openalex-snapshot
Speculative Privacy Tracking (SPT): Leaking Information From Speculative Execution Without Compromising Privacy
inferredcites →https://doi.org/10.1145/3489517openalex-snapshot
Proceedings of the 59th ACM/IEEE Design Automation Conference
inferredcites →https://doi.org/10.1145/605397openalex-snapshot
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
inferredcites →https://doi.org/10.60882/cispa.24612762openalex-snapshot
Ret2Spec: Speculative Execution Using Return Stack Buffers

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-93254-0_8openalex-snapshot
S-TSG: Description Model of Transient Execution Attacks in Intel SGX
inferred← citeshttps://doi.org/10.1007/978-3-032-00627-1_9openalex-snapshot
Exploring Speculation Barriers for RISC-V Selective Speculation
inferred← citeshttps://doi.org/10.1007/978-981-95-4674-9_22openalex-snapshot
Analyzing and Mitigating the SSB Vulnerability in an MDP-Equipped RISC-V Processor
inferred← citeshttps://doi.org/10.1016/j.cose.2025.104817openalex-snapshot
Attacks, defenses and perspectives for the runtime security of RISC-V IoT devices: A review
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103875openalex-snapshot
RA scoreboarding: Return address stack protection in RISC-V
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240638openalex-snapshot
SpectrePrefetch: Undermining Cache-Centric Secure Speculation with Modern Hardware Prefetchers
inferred← citeshttps://doi.org/10.1109/iccd58817.2023.00093openalex-snapshot
Architectural Contracts for Safe Speculation
inferred← citeshttps://doi.org/10.1109/icicnct66124.2025.11233140openalex-snapshot
Java Platform Security: a Behavioral Model for Speculative Execution Vulnerabilities
inferred← citeshttps://doi.org/10.1109/ispa-bdcloud-socialcom-sustaincom59178.2023.00089openalex-snapshot
DPFCFI: A Hardware-Based Forward Control-Flow Integrity for Architecture and Microarchitecture
inferred← citeshttps://doi.org/10.1109/sbac-pad63648.2024.00011openalex-snapshot
JANUS: A Simple and Efficient Speculative Defense using Reinforcement Learning
inferred← citeshttps://doi.org/10.1109/tifs.2025.3598478openalex-snapshot
SCSGuardian: A Practical Hardware Defense Against Speculative Cache Side-Channel Attacks
inferred← citeshttps://doi.org/10.1145/3695053.3731119openalex-snapshot
SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization
inferred← citeshttps://doi.org/10.1145/3725843.3756074openalex-snapshot
ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes
inferred← citeshttps://doi.org/10.1145/3734218openalex-snapshot
A Survey of Side-Channel Attacks on Branch Prediction Units
inferred← citeshttps://doi.org/10.3390/electronics14203973openalex-snapshot
TrackRISC: An Implicit Attack Flow Model and Hardware Microarchitectural Mitigation for Speculative Cache-Based Covert Channels
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