On the public citation graph

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

https://doi.org/10.1145/3490422
0 signed · 34 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-981-96-2697-7_12openalex-snapshot
Enhanced Tuberculosis Detection Using Deep Neural Network on Microscopic Images
inferred← citeshttps://doi.org/10.1016/b978-012170960-0/50067-0openalex-snapshot
VLSI Signal Processing
inferred← citeshttps://doi.org/10.1016/b978-012370522-8.50008-xopenalex-snapshot
Reconfiguration Management
inferred← citeshttps://doi.org/10.1016/b978-012370522-8.50010-8openalex-snapshot
Compute Models and System Architectures
inferred← citeshttps://doi.org/10.1016/b978-012370522-8.50012-1openalex-snapshot
Compiling C for Spatial Computing
inferred← citeshttps://doi.org/10.1016/j.asoc.2005.10.002openalex-snapshot
A novel approach to the placement and routing problems for field programmable gate arrays
inferred← citeshttps://doi.org/10.1016/j.cpc.2023.108997openalex-snapshot
Hardware acceleration of complex HEP algorithms with HLS and FPGAs: Methodology and preliminary implementation
inferred← citeshttps://doi.org/10.1016/j.engappai.2023.107611openalex-snapshot
Enabling global interpolation, derivative estimation and model identification from sparse multi-experiment time series data via neural ODEs
inferred← citeshttps://doi.org/10.1016/j.future.2025.107728openalex-snapshot
Efficient Number Theoretic Transform accelerator on the versal platform powered by the AI Engine
inferred← citeshttps://doi.org/10.1016/j.micpro.2005.07.001openalex-snapshot
Flowpaths: Compiling stack-based IR to hardware
inferred← citeshttps://doi.org/10.1016/j.microc.2025.113395openalex-snapshot
Next-generation microfluidics based on artificial intelligence: Applications for food sample analysis
inferred← citeshttps://doi.org/10.1016/j.neucom.2025.130417openalex-snapshot
Vision transformers on the edge: A comprehensive survey of model compression and acceleration strategies
inferred← citeshttps://doi.org/10.1016/s0097-8493(96)00083-0openalex-snapshot
Implementations of Cube-4 on the Teramac custom computing machine
inferred← citeshttps://doi.org/10.1016/s0141-9331(97)00023-9openalex-snapshot
A quantitative analysis of the benefits of the use of area-I/O pads in FPGAs
inferred← citeshttps://doi.org/10.1109/iccrd54409.2022.9730377openalex-snapshot
A Survey on Convolutional Neural Network Accelerators: GPU, FPGA and ASIC
inferred← citeshttps://doi.org/10.1117/12.2677688openalex-snapshot
Custom precision accelerators for energy-efficient image-to-image transformations in motion picture workflows
inferred← citeshttps://doi.org/10.1145/3404555.3404626openalex-snapshot
A High Energy-Efficiency Inference Accelerator Exploiting Sparse CNNs
inferred← citeshttps://doi.org/10.1145/3561514openalex-snapshot
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis
inferred← citeshttps://doi.org/10.1145/3572547openalex-snapshot
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs
inferred← citeshttps://doi.org/10.1145/3579371.3589054openalex-snapshot
SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM
inferred← citeshttps://doi.org/10.1145/3593025openalex-snapshot
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration
inferred← citeshttps://doi.org/10.1145/3597417openalex-snapshot
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns
inferred← citeshttps://doi.org/10.1145/3613424.3623790openalex-snapshot
HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator
inferred← citeshttps://doi.org/10.1145/3617685openalex-snapshot
RACE: An Efficient Redundancy-aware Accelerator for Dynamic Graph Neural Network
inferred← citeshttps://doi.org/10.1145/3620666.3651336openalex-snapshot
FEASTA: A Flexible and Efficient Accelerator for Sparse Tensor Algebra in Machine Learning
inferred← citeshttps://doi.org/10.1145/3656177openalex-snapshot
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference
inferred← citeshttps://doi.org/10.1145/3662000openalex-snapshot
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs
inferred← citeshttps://doi.org/10.1145/3676536.3676771openalex-snapshot
A Processing-using-Memory Architecture for Commodity DRAM Devices with Enhanced Compatibility and Reliability
inferred← citeshttps://doi.org/10.1145/3701728openalex-snapshot
Efficient Deep Learning Infrastructures for Embedded Computing Systems: A Comprehensive Survey and Future Envision
inferred← citeshttps://doi.org/10.1145/3708035.3736086openalex-snapshot
Real-Time In-Network Machine Learning on P4-Programmable FPGA SmartNICs with Fixed-Point Arithmetic and Taylor Approximations
inferred← citeshttps://doi.org/10.1145/3759458openalex-snapshot
HMSA: High-Performance Heterogeneous Mixed-Precision CNN Systolic Array Accelerator on FPGA
inferred← citeshttps://doi.org/10.1145/3769307openalex-snapshot
Holistic Optimization Framework for FPGA Accelerators
inferred← citeshttps://doi.org/10.1145/3771288openalex-snapshot
CD-LLM: A Heterogeneous Multi-FPGA System for Batched Decoding of 70B+ LLMs Using a Compute-Dedicated Architecture
inferred← citeshttps://doi.org/10.1145/606603.606605openalex-snapshot
Analysis of FPGA/FPIC switch modules
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.