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RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration

https://doi.org/10.1145/3593025
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform
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Theory of latency-insensitive design
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HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping
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Towards Synthesis-Free JIT Compilation to Commodity FPGAs
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Latte: Locality Aware Transformation for High-Level Synthesis
inferredcites →https://doi.org/10.1109/fccm.2018.00030openalex-snapshot
RapidWright: Enabling Custom Crafted Implementations for FPGAs
inferredcites →https://doi.org/10.1109/fccm32419.2014openalex-snapshot
2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines
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2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines
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2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
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FANS: FPGA-Accelerated Near-Storage Sorting
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TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs
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FPGA Accelerated FPGA Placement
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2013 23rd International Conference on Field programmable Logic and Applications
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2016 26th International Conference on Field Programmable Logic and Applications (FPL)
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2019 29th International Conference on Field Programmable Logic and Applications (FPL)
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2020 30th International Conference on Field-Programmable Logic and Applications (FPL)
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2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)
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PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess
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Deterministic multi-core parallel routing for FPGAs
inferredcites →https://doi.org/10.1109/fpt.2012.6412110openalex-snapshot
FPGA optimized packet-switched NoC using split and merge primitives
inferredcites →https://doi.org/10.1109/fpt.2014.7082746openalex-snapshot
Design re-use for compile time reduction in FPGA high-level synthesis flows
inferredcites →https://doi.org/10.1109/iccad33900.2014openalex-snapshot
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/iccad39534.2017openalex-snapshot
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942077openalex-snapshot
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/icfpt47387.2019.00026openalex-snapshot
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks
inferredcites →https://doi.org/10.1109/icfpt47387.2019.00028openalex-snapshot
An Open-Source Lightweight Timing Model for RapidWright
inferredcites →https://doi.org/10.1109/icfpt51103.2020.00035openalex-snapshot
Fast Linking of Separately-Compiled FPGA Blocks without a NoC
inferredcites →https://doi.org/10.1109/icfpt52863.2021openalex-snapshot
2021 International Conference on Field-Programmable Technology (ICFPT)
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Proceedings of 9th International Parallel Processing Symposium
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2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)
inferredcites →https://doi.org/10.1109/proc.1987.13876openalex-snapshot
Synchronous data flow
inferredcites →https://doi.org/10.1109/reconfig48160.2019openalex-snapshot
2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
inferredcites →https://doi.org/10.1109/rtcsa41688.2017openalex-snapshot
2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
inferredcites →https://doi.org/10.1109/tcad.1985.1270101openalex-snapshot
A Procedure for Placement of Standard-Cell VLSI Circuits
inferredcites →https://doi.org/10.1109/tcad.2011.2165715openalex-snapshot
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010
inferredcites →https://doi.org/10.1109/tcad.2017.2768416openalex-snapshot
A Runtime Optimization Approach for FPGA Routing
inferredcites →https://doi.org/10.1109/tetc.2022.3228575openalex-snapshot
TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs
inferredcites →https://doi.org/10.1145/1024393openalex-snapshot
Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
inferredcites →https://doi.org/10.1145/1055137.1055177openalex-snapshot
Multilevel generalized force-directed method for circuit placement
inferredcites →https://doi.org/10.1145/1117201openalex-snapshot
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
inferredcites →https://doi.org/10.1145/1344671.1344676openalex-snapshot
High-quality, deterministic parallel placement for FPGAs on commodity hardware
inferredcites →https://doi.org/10.1145/1450135openalex-snapshot
Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
inferredcites →https://doi.org/10.1145/1687399.1687525openalex-snapshot
Parallel multi-level analytical global placement on graphics processing units
inferredcites →https://doi.org/10.1145/2145694.2145703openalex-snapshot
CONNECT
inferredcites →https://doi.org/10.1145/2617593openalex-snapshot
VTR 7.0
inferredcites →https://doi.org/10.1145/2684746openalex-snapshot
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
inferredcites →https://doi.org/10.1145/2744769openalex-snapshot
Proceedings of the 52nd Annual Design Automation Conference
inferredcites →https://doi.org/10.1145/2966986openalex-snapshot
Proceedings of the 35th International Conference on Computer-Aided Design
inferredcites →https://doi.org/10.1145/3027486openalex-snapshot
Hoplite
inferredcites →https://doi.org/10.1145/3174243.3174255openalex-snapshot
Rosetta
inferredcites →https://doi.org/10.1145/3174243.3174264openalex-snapshot
Dynamically Scheduled High-level Synthesis
inferredcites →https://doi.org/10.1145/3289602.3293906openalex-snapshot
Xilinx Adaptive Compute Acceleration Platform
inferredcites →https://doi.org/10.1145/3373087.3375297openalex-snapshot
Combining Dynamic & Static Scheduling in High-level Synthesis
inferredcites →https://doi.org/10.1145/3406959openalex-snapshot
Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization
inferredcites →https://doi.org/10.1145/3431920openalex-snapshot
The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
inferredcites →https://doi.org/10.1145/3431920.3439290openalex-snapshot
ThunderGP
inferredcites →https://doi.org/10.1145/3445814.3446699openalex-snapshot
When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs
inferredcites →https://doi.org/10.1145/3469660openalex-snapshot
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects
inferredcites →https://doi.org/10.1145/3490422openalex-snapshot
Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
inferredcites →https://doi.org/10.1145/3490422.3502335openalex-snapshot
HiPR
inferredcites →https://doi.org/10.1145/3490422.3502357openalex-snapshot
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication
inferredcites →https://doi.org/10.1145/3491236openalex-snapshot
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs
inferredcites →https://doi.org/10.1145/3503222.3507740openalex-snapshot
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development
inferredcites →https://doi.org/10.1145/3524108openalex-snapshot
Democratizing Domain-Specific Computing
inferredcites →https://doi.org/10.1145/3530775openalex-snapshot
FPGA HLS Today: Successes, Challenges, and Opportunities
inferredcites →https://doi.org/10.1145/775832.775984openalex-snapshot
Fast timing-driven partitioning-based placement for island style FPGAs
inferredcites →https://doi.org/10.23919/date.2019.8714724openalex-snapshot
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
inferredcites →https://doi.org/10.23919/date42667.2018openalex-snapshot
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
inferredcites →https://doi.org/10.48550/arxiv.2111.12555openalex-snapshot
Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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AffiNiTy: A Multi-Scalar Multiplication Accelerator with a Novel Batched Inversion Architecture
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323739openalex-snapshot
Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling
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Decentralizing Compressed Sensing for Federated Learning with Hardware–Software Codesign
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REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs
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Modularity Driven Parallel Placement Algorithm for 2.5D FPGA Architectures
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REFRESH FPGAs: Sustainable FPGA Chiplet Architectures
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LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA Architectures
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Reconfigurable Stream Network Architecture
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Misam: Machine Learning Assisted Dataflow Selection in Accelerators for Sparse Matrix Multiplication
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Algorithmic-Level Design Partitioning for Latency Minimization in Multi-Chip and Multi-Die Systems
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RND: A Mixed-Grained Parallel Routing Framework with R egion-based N et D ecomposition for UltraScale FPGAs
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Holistic Optimization Framework for FPGA Accelerators
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Advanced Timing Closure Techniques in Full Chip Integration of Adaptive SoCs
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Design exploration of machine learning data-flows onto heterogeneous reconfigurable hardware
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