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Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_7openalex-snapshot
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
inferredcites →https://doi.org/10.1007/bf01407835openalex-snapshot
Some efficient solutions to the affine scheduling problem. I. One-dimensional time
inferredcites →https://doi.org/10.1007/s10617-012-9096-8openalex-snapshot
An overview of today’s high-level synthesis tools
inferredcites →https://doi.org/10.1109/access.2020.3012084openalex-snapshot
A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective
inferredcites →https://doi.org/10.1109/codesisss51650.2020.9244033openalex-snapshot
Proceedings of the 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
inferredcites →https://doi.org/10.1109/fccm51124.2021.00030openalex-snapshot
Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs
inferredcites →https://doi.org/10.1109/fpga.1996.564808openalex-snapshot
MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources
inferredcites →https://doi.org/10.1109/fpl53798.2021.00074openalex-snapshot
HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler
inferredcites →https://doi.org/10.1109/hpca51647.2021.00042openalex-snapshot
Ultra-Elastic CGRAs for Irregular Loop Specialization
inferredcites →https://doi.org/10.1109/iccad.2013.6691121openalex-snapshot
SDC-based modulo scheduling for pipeline synthesis
inferredcites →https://doi.org/10.1109/isca.2016.30openalex-snapshot
EIE: Efficient Inference Engine on Compressed Deep Neural Network
inferredcites →https://doi.org/10.1109/isca52012.2021.00085openalex-snapshot
SARA: Scaling a Reconfigurable Dataflow Accelerator
inferredcites →https://doi.org/10.1109/jssc.2016.2616357openalex-snapshot
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/tvlsi.2012.2207748openalex-snapshot
BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture
inferredcites →https://doi.org/10.1109/tvlsi.2018.2797600openalex-snapshot
Stream Processing Dual-Track CGRA for Object Inference
inferredcites →https://doi.org/10.1145/1375581.1375595openalex-snapshot
A practical automatic polyhedral parallelizer and locality optimizer
inferredcites →https://doi.org/10.1145/143095openalex-snapshot
Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation - PLDI '92
inferredcites →https://doi.org/10.1145/2435264.2435271openalex-snapshot
Improving high level synthesis optimization opportunity through polyhedral transformations
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2897824.2925952openalex-snapshot
Automatically scheduling halide image processing pipelines
inferredcites →https://doi.org/10.1145/2967938.2967969openalex-snapshot
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs
inferredcites →https://doi.org/10.1145/3107953openalex-snapshot
Programming Heterogeneous Systems from an Image Processing DSL
inferredcites →https://doi.org/10.1145/3174243.3174251openalex-snapshot
Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing Kernels
inferredcites →https://doi.org/10.1145/3192366.3192379openalex-snapshot
Spatial: a language and compiler for application accelerators
inferredcites →https://doi.org/10.1145/3229762.3229766openalex-snapshot
Leveraging the VTA-TVM Hardware-Software Stack for FPGA Acceleration of 8-bit ResNet-18 Inference
inferredcites →https://doi.org/10.1145/3306346.3322967openalex-snapshot
Learning to optimize halide with tree search and random programs
inferredcites →https://doi.org/10.1145/3494534openalex-snapshot
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
inferredcites →https://doi.org/10.1145/3519939.3523446openalex-snapshot
Exocompilation for productive programming of hardware accelerators
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-981-96-6005-6_17openalex-snapshot
ADMEdge: Accelerating Edge Computing Through Co-design for Enhanced Data Mobility
inferred← citeshttps://doi.org/10.1007/s13246-025-01548-8openalex-snapshot
Accelerated inference for thyroid nodule recognition in ultrasound imaging using FPGA
inferred← citeshttps://doi.org/10.1109/access.2023.3345660openalex-snapshot
SlidingConv: Domain-Specific Description of Sliding Discrete Cosine Transform Convolution for Halide
inferred← citeshttps://doi.org/10.1109/access.2024.3390564openalex-snapshot
Hardware Design of Lightweight Binary Classification Algorithms for Small-Size Images on FPGA
inferred← citeshttps://doi.org/10.1109/iscas46773.2023.10182052openalex-snapshot
An Open-Source $4 \times 8$ Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow
inferred← citeshttps://doi.org/10.1109/iseda65950.2025.11100357openalex-snapshot
An Agile Design Method for Reconfigurable Spatial Accelerators in Tensor Computation
inferred← citeshttps://doi.org/10.1109/jssc.2023.3313116openalex-snapshot
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
inferred← citeshttps://doi.org/10.1109/jssc.2025.3604724openalex-snapshot
Onyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications
inferred← citeshttps://doi.org/10.1109/tcad.2024.3390542openalex-snapshot
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
inferred← citeshttps://doi.org/10.1109/tcad.2024.3445810openalex-snapshot
GOURD: Tensorizing Streaming Applications to Generate Multi-Instance Compute Platforms
inferred← citeshttps://doi.org/10.1145/3617232.3624850openalex-snapshot
HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3656019.3676896openalex-snapshot
Mozart: Taming Taxes and Composing Accelerators with Shared-Memory
inferred← citeshttps://doi.org/10.1145/3676849openalex-snapshot
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
inferred← citeshttps://doi.org/10.1145/3695053.3731044openalex-snapshot
HYTE: Flexible Tiling for Sparse Accelerators via Hybrid Static-Dynamic Approaches
inferred← citeshttps://doi.org/10.1145/3696443.3708918openalex-snapshot
Stardust: Compiling Sparse Tensor Algebra to a Reconfigurable Dataflow Architecture
inferred← citeshttps://doi.org/10.1145/3733721openalex-snapshot
DVHetero: A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA
inferred← citeshttps://doi.org/10.1145/3787109.3815253openalex-snapshot
An Agile Design Framework for Resource-Efficient and Parameterizable Edge ISPs
inferred← citeshttps://doi.org/10.1145/3787109.3815269openalex-snapshot
PoSVM: Posit-Based Accelerator for SVM-driven Edge Biomedical Image Classification
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