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AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4020-8588-8_6openalex-snapshot
AutoPilot: A Platform-Based ESL Synthesis System
inferredcites →https://doi.org/10.1007/978-3-319-26408-0_8openalex-snapshot
Source-to-Source Optimization for HLS
inferredcites →https://doi.org/10.1007/s10472-010-9213-yopenalex-snapshot
Analyzing bandit-based adaptive operator selection mechanisms
inferredcites →https://doi.org/10.1016/0022-2836(70)90057-4openalex-snapshot
A general method applicable to the search for similarities in the amino acid sequence of two proteins
inferredcites →https://doi.org/10.1049/iet-cdt.2011.0115openalex-snapshot
Machine learning predictive modelling high-level synthesis design space exploration
inferredcites →https://doi.org/10.1088/1748-0221/13/07/p07027openalex-snapshot
Fast inference of deep neural networks in FPGAs for particle physics
inferredcites →https://doi.org/10.1109/99.660313openalex-snapshot
OpenMP: an industry standard API for shared-memory programming
inferredcites →https://doi.org/10.1109/access.2017.2727221openalex-snapshot
Design Space Exploration of LDPC Decoders Using High-Level Synthesis
inferredcites →https://doi.org/10.1109/dac.2018.8465940openalex-snapshot
Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture
inferredcites →https://doi.org/10.1109/eslsyn.2014.6850383openalex-snapshot
Machine-learning based simulated annealer method for high level synthesis design space exploration
inferredcites →https://doi.org/10.1109/fccm.2018.00029openalex-snapshot
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
inferredcites →https://doi.org/10.1109/fccm48280.2020.00032openalex-snapshot
Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies
inferredcites →https://doi.org/10.1109/iccd.2014.6974719openalex-snapshot
Design space exploration of multiple loops on FPGAs using high level synthesis
inferredcites →https://doi.org/10.1109/iccd.2018.00040openalex-snapshot
Lattice-Traversing Design Space Exploration for High Level Synthesis
inferredcites →https://doi.org/10.1109/iccd46524.2019.00024openalex-snapshot
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/iiswc.2014.6983050openalex-snapshot
MachSuite: Benchmarks for accelerator design and customized architectures
inferredcites →https://doi.org/10.1109/ipdpsw.2019.00028openalex-snapshot
Pareto Optimal Design Space Exploration for Accelerated CNN on FPGA
inferredcites →https://doi.org/10.1109/jssc.1974.1050511openalex-snapshot
Design of ion-implanted MOSFET's with very small physical dimensions
inferredcites →https://doi.org/10.1109/sc.2004.61openalex-snapshot
Towards a Systematic, Pragmatic and Architecture-Aware Program Optimization Process for Complex Processors
inferredcites →https://doi.org/10.1109/tcad.2011.2110592openalex-snapshot
High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1109/tcad.2014.2363392openalex-snapshot
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis
inferredcites →https://doi.org/10.1109/tetc.2018.2794068openalex-snapshot
Cluster-Based Heuristic for High Level Synthesis Design Space Exploration
inferredcites →https://doi.org/10.1145/1055137.1055177openalex-snapshot
Multilevel generalized force-directed method for circuit placement
inferredcites →https://doi.org/10.1145/2209291.2209302openalex-snapshot
Divide and conquer high-level synthesis design space exploration
inferredcites →https://doi.org/10.1145/2463209.2488795openalex-snapshot
On learning-based methods for design-space exploration with high-level synthesis
inferredcites →https://doi.org/10.1145/2678373.2665678openalex-snapshot
A reconfigurable fabric for accelerating large-scale datacenter services
inferredcites →https://doi.org/10.1145/2872362.2872415openalex-snapshot
Generating Configurable Hardware from Parallel Patterns
inferredcites →https://doi.org/10.1145/2934583.2953984openalex-snapshot
Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers
inferredcites →https://doi.org/10.1145/2980024.2872415openalex-snapshot
Generating Configurable Hardware from Parallel Patterns
inferredcites →https://doi.org/10.1145/3007787.3001150openalex-snapshot
Automatic generation of efficient accelerators for reconfigurable hardware
inferredcites →https://doi.org/10.1145/3020078.3021747openalex-snapshot
A Parallel Bandit-Based Approach for Autotuning FPGA Compilation
inferredcites →https://doi.org/10.1145/3041219openalex-snapshot
Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies
inferredcites →https://doi.org/10.1145/3065386openalex-snapshot
ImageNet classification with deep convolutional neural networks
inferredcites →https://doi.org/10.1145/3174243.3174248openalex-snapshot
Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL
inferredcites →https://doi.org/10.1145/3240765.3240815openalex-snapshot
HLS-based optimization and design space exploration for applications with variable loop bounds
inferredcites →https://doi.org/10.1145/3296979.3192397openalex-snapshot
GPU code optimization using abstract kernel emulation and sensitivity analysis
inferredcites →https://doi.org/10.1145/3316781.3317754openalex-snapshot
Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration
inferredcites →https://doi.org/10.1145/3373087.3375321openalex-snapshot
End-to-End Optimization of Deep Learning Applications
inferredcites →https://doi.org/10.1145/3385412.3385974openalex-snapshot
Predictable accelerator design with time-sensitive affine types
inferredcites →https://doi.org/10.23919/date.2017.7927161openalex-snapshot
Design Space exploration of FPGA-based accelerators with multi-level parallelism
inferredcites →https://doi.org/10.23919/date51398.2021.9474241openalex-snapshot
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design
inferredcites →https://doi.org/10.48550/arxiv.1502.05700openalex-snapshot
Scalable Bayesian Optimization Using Deep Neural Networks
inferredcites →https://doi.org/10.48550/arxiv.2001.03535openalex-snapshot
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs
inferredcites →https://doi.org/10.5281/zenodo.5680908openalex-snapshot
fastmachinelearning/hls4ml: coris
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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AI-Driven Optimization Frameworks for Intelligent VLSI Systems: A Networked and System-Level Perspective
inferred← citeshttps://doi.org/10.1007/978-3-032-35251-4_27openalex-snapshot
Two-Stage Hierarchy-Aware Learning with Gradient Conflict Mitigation for HLS Latency and Resource Prediction
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A Unified Synthesis Framework for Dataflow Accelerators Through Multi-level Software and Hardware Intermediate Representations
inferred← citeshttps://doi.org/10.1007/s13369-022-07177-7openalex-snapshot
N-PIR: A Neighborhood-Based Pareto Iterative Refinement Approach for High-Level Synthesis
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Federated deep learning and explainable AI for real-time credit card fraud detection in highly imbalanced transaction streams
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A novel machine learning-driven optimization methodology for faster and more efficient design space exploration in high-level synthesis
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High Level Synthesis in the Agentic Era
inferred← citeshttps://doi.org/10.1016/j.vlsi.2026.102901openalex-snapshot
FICS: A machine learning-based feasibility inference classifier for accelerating simulated annealing in energy- and reliability-aware high-level synthesis
inferred← citeshttps://doi.org/10.1109/access.2022.3201107openalex-snapshot
High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks
inferred← citeshttps://doi.org/10.1109/access.2023.3252002openalex-snapshot
Casper: Accelerating Stencil Computations Using Near-Cache Processing
inferred← citeshttps://doi.org/10.1109/access.2025.3602232openalex-snapshot
Automated Hardware Design Methodology for Digital Filters With High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/access.2025.3605852openalex-snapshot
AnnotationGym: A Generic Framework for Automatic Source Code Annotation
inferred← citeshttps://doi.org/10.1109/asp-dac58780.2024.10473961openalex-snapshot
Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets
inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420389openalex-snapshot
FESTAL: Dataflow Accelerator Synthesis Framework with Graph-Based Fusion for FPGA
inferred← citeshttps://doi.org/10.1109/coins65080.2025.11125726openalex-snapshot
TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization
inferred← citeshttps://doi.org/10.1109/csat61646.2023.00065openalex-snapshot
Design and Simulation of FIR Digital Filter Under FPGA
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247880openalex-snapshot
Lightning Talk: The Next Wave of High-level Synthesis
inferred← citeshttps://doi.org/10.1109/fccm57271.2023.00053openalex-snapshot
OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference
inferred← citeshttps://doi.org/10.1109/fccm60383.2024.00057openalex-snapshot
Ph.D. Project: Modernizing High-Level Hardware Design Workflows
inferred← citeshttps://doi.org/10.1109/fccm68464.2026.00060openalex-snapshot
LENS-HLS: LLM-Enhanced Learning-based Design Space Exploration for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fccm68464.2026.00079openalex-snapshot
Reconfigurable Computing Challenge: RapidScan High-Throughput Parameterized HLS-based Streaming String Matching Library for FPGAs
inferred← citeshttps://doi.org/10.1109/fpl68686.2025.00017openalex-snapshot
DEFA: Design Space Exploration for FPGA Overlay Accelerators Through Frequency Prediction and Bayesian Optimization
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00060openalex-snapshot
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
inferred← citeshttps://doi.org/10.1109/icassp43922.2022.9746473openalex-snapshot
PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323853openalex-snapshot
Robust GNN-Based Representation Learning for HLS
inferred← citeshttps://doi.org/10.1109/iccd58817.2023.00089openalex-snapshot
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
inferred← citeshttps://doi.org/10.1109/icfpt59805.2023.00017openalex-snapshot
HGBO-DSE: Hierarchical GNN and Bayesian Optimization based HLS Design Space Exploration
inferred← citeshttps://doi.org/10.1109/iclad65226.2025.00013openalex-snapshot
Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
inferred← citeshttps://doi.org/10.1109/ipdpsw66978.2025.00119openalex-snapshot
FGI: Fast GNN Inference on Multi-Core Systems
inferred← citeshttps://doi.org/10.1109/iscas66217.2026.11562269openalex-snapshot
Performance Pragma-Based Design Space Pruning and Exploration for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/iscas66217.2026.11562547openalex-snapshot
ViMA: A Decoupled FPGA Accelerator for Vision Mamba with Resource-Space Exploration
inferred← citeshttps://doi.org/10.1109/les.2023.3330610openalex-snapshot
CollectiveHLS: Ultrafast Knowledge-Based HLS Design Optimization
inferred← citeshttps://doi.org/10.1109/les.2024.3446797openalex-snapshot
Enhancing HLS Performance Prediction on FPGAs Through Multimodal Representation Learning
inferred← citeshttps://doi.org/10.1109/les.2025.3600555openalex-snapshot
Toward Efficient FPGA Accelerator DSE via Hierarchical and RM-Guided Methods
inferred← citeshttps://doi.org/10.1109/mcas.2026.3662307openalex-snapshot
Report for NSF Workshop on AI for Electronic Design Automation [NSF Workshop Report]
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00018openalex-snapshot
OverGen: Improving FPGA Usability through Domain-specific Overlay Generation
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00062openalex-snapshot
Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/mlcad62225.2024.10740204openalex-snapshot
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/mlcad62225.2024.10740257openalex-snapshot
Learning to Compare Hardware Designs for High-Level Synthesis
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Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models
inferred← citeshttps://doi.org/10.1109/tc.2026.3688303openalex-snapshot
DTRRS: A Dynamic Task Real-Time Reconfiguration and Scheduling Architecture for FPGAs in Embedded Systems
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EvoPlace: Evolution of Optimization Algorithms for Global Placement via Large Language Models
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Harnessing GNNs for Robust Representation Learning in High-Level Synthesis
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PIPP: A Practical PUF-Based Intellectual Property Protection Scheme for DNN Model on FPGA
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LOGO-Based Intellectual Property Right Protection Scheme for GANs on FPGA
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A Survey of FPGA Optimization Methods for Data Center Energy Efficiency
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Automated accelerator optimization aided by graph neural networks
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Democratizing Domain-Specific Computing
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FPGA HLS Today: Successes, Challenges, and Opportunities
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FADO: F loorplan- A ware D irective O ptimization for High-Level Synthesis Designs on Multi-Die FPGAs
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Early DSE and Automatic Generation of Coarse-grained Merged Accelerators
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GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design
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Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators
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AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis
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SPARTA: Spatial Acceleration for Efficient and Scalable Horizontal Diffusion Weather Stencil Computation
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HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
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Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis
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HLS Taking Flight: Toward Using High-Level Synthesis Techniques in a Space-Borne Instrument
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Data-driven HLS optimization for reconfigurable accelerators
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FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs
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HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures
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Learning to Compare Hardware Designs for High-Level Synthesis
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Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis
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Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models
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Efficient Task Transfer for HLS DSE
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HLSPilot: LLM-based High-Level Synthesis
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Balor: HLS Source Code Evaluator Based on Custom Graphs and Hierarchical GNNs
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PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
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Assassyn: A Unified Abstraction for Architectural Simulation and Implementation
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CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design Optimization
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A Unified Framework for Automated Code Transformation and Pragma Insertion
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Stream-HLS: Towards Automatic Dataflow Acceleration
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Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
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Maximizing Data and Hardware Reuse for HLS with Early-Stage Symbolic Partitioning
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ML4SODA: A Decision Tree Guided Design Space Exploration for Fast and High Quality MLIR-based HLS
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DFlows : A Flow-Based Programming Approach for a Polyglot Design-Space Exploration Framework
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Productively Generating a High-Performance Linear Algebra Library on FPGAs
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HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis
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Automated FPGA Accelerator Generation Framework for Transformers with Dataflow Optimization
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A Taxonomy of the High-Level Synthesis Ecosystem for Heterogeneous FPGA Systems
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Chiplet Design Automation: Methodologies, Advances, and Directions
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GNΩSIS: Lessons Learned in Generating a High-Level Synthesis Dataset
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Towards High-Performance Flexible FPGA-Based Accelerators for CNN Inference: General Hardware Architecture and End-to-End Deploying Toolflow
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A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware
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A Functional Approach to Synthesizing Routable Programmable Accelerators for Neural Networks
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An Efficient Design Space Exploration Framework for FPGA Overlay Accelerators through Frequency Prediction and Bayesian Optimization
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Focus Session: Stepping Stones Towards Domain Acceleration Using AI-Driven High-Level Synthesis Design
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Analysis of Research Progress on Deployment Methods for Deep Learning Models on FPGAs
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Compiler Technologies in Deep Learning Co-Design: A Survey
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Bring Your Own Codegen to Deep Learning Compiler
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Automating the derivation of memory allocations for acceleration of polyhedral programs
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