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Loop Rerolling for Hardware Decompilation

https://doi.org/10.1145/3591237
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-48194-x_17openalex-snapshot
Linear-Time Longest-Common-Prefix Computation in Suffix Arrays and Its Applications
inferredcites →https://doi.org/10.1007/978-3-319-23467-0_15openalex-snapshot
Instruction Level Loop De-optimization
inferredcites →https://doi.org/10.1007/978-3-642-16478-1_2openalex-snapshot
Introducing Kansas Lava
inferredcites →https://doi.org/10.1007/s10009-002-0086-1openalex-snapshot
Higher-level techniques for hardware description and synthesis
inferredcites →https://doi.org/10.1007/s10009-012-0249-7openalex-snapshot
Program sketching
inferredcites →https://doi.org/10.1016/s0304-3975(01)00121-9openalex-snapshot
Simple and flexible detection of contiguous repeats using a suffix tree
inferredcites →https://doi.org/10.1109/access.2019.2901949openalex-snapshot
A Comprehensive FPGA Reverse Engineering Tool-Chain: From Bitstream to RTL Code
inferredcites →https://doi.org/10.1109/asianhost47458.2019.9006699openalex-snapshot
RERTL: Finite State Transducer Logic Recovery at Register Transfer Level
inferredcites →https://doi.org/10.1109/asp-dac36859.2016openalex-snapshot
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)
inferredcites →https://doi.org/10.1109/cgo53902.2022.9741256openalex-snapshot
Loop Rolling for Code Size Reduction
inferredcites →https://doi.org/10.1109/fmcad.2014.6987599openalex-snapshot
Template-based circuit understanding
inferredcites →https://doi.org/10.1109/fmcad.2015.7542265openalex-snapshot
Simulation graphs for reverse engineering
inferredcites →https://doi.org/10.1109/host20890.2012openalex-snapshot
2012 IEEE International Symposium on Hardware-Oriented Security and Trust
inferredcites →https://doi.org/10.1109/host33780.2014openalex-snapshot
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)
inferredcites →https://doi.org/10.1109/iccad39534.2017openalex-snapshot
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/ipdps.2002.1016653openalex-snapshot
Overview of hydra: a concurrent language for synchronous digital circuit design
inferredcites →https://doi.org/10.1109/iscas.2004.1328657openalex-snapshot
Proceedings of 2004 IEEE International Symposium on Circuits and Systems
inferredcites →https://doi.org/10.1109/iscas30516.2016openalex-snapshot
2016 IEEE International Symposium on Circuits and Systems (ISCAS)
inferredcites →https://doi.org/10.1109/mm.2020.2997639openalex-snapshot
A Case for Accelerating Software RTL Simulation
inferredcites →https://doi.org/10.1109/tcad.2006.881335openalex-snapshot
A High-Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization
inferredcites →https://doi.org/10.1109/tetc.2013.2294918openalex-snapshot
Reverse Engineering Digital Circuits Using Structural and Functional Analyses
inferredcites →https://doi.org/10.1109/tse.2002.1019480openalex-snapshot
CCFinder: a multilinguistic token-based code clone detection system for large scale source code
inferredcites →https://doi.org/10.1109/wcre.1995.514697openalex-snapshot
On finding duplication and near-duplication in large software systems
inferredcites →https://doi.org/10.1145/1168857.1168907openalex-snapshot
Combinatorial sketching for finite programs
inferredcites →https://doi.org/10.1145/1233501openalex-snapshot
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design - ICCAD '06
inferredcites →https://doi.org/10.1145/19551.19541openalex-snapshot
URPR—An extension of URCR for software pipelining
inferredcites →https://doi.org/10.1145/2666356.2594340openalex-snapshot
A lightweight symbolic virtual machine for solver-aided host languages
inferredcites →https://doi.org/10.1145/291251.289440openalex-snapshot
Lava
inferredcites →https://doi.org/10.1145/3193121openalex-snapshot
Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs
inferredcites →https://doi.org/10.1145/3276519openalex-snapshot
Finding code that explodes under symbolic evaluation
inferredcites →https://doi.org/10.1145/3815481openalex-snapshot
egg: Fast and Extensible Equality Saturation
inferredcites →https://doi.org/10.1145/800145openalex-snapshot
Proceedings of the 9th annual workshop on Microprogramming - MICRO 9
inferredcites →https://doi.org/10.23919/fpl.2017.8056860openalex-snapshot
A pythonic approach for rapid hardware prototyping and instrumentation
inferredcites →https://doi.org/10.5281/zenodo.7686503openalex-snapshot
Loop Rerolling For Hardware Decompilation artifact
inferredcites →https://doi.org/10.7873/date.2014.165openalex-snapshot
SKETCHILOG: Sketching combinational circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Enhancing LLM to Decompile Optimized PTX to Readable CUDA for Tensor Programs
inferred← citeshttps://doi.org/10.1109/cgo68049.2026.11395195openalex-snapshot
Eliminating Redundancy: Ultra-compact Code Generation for Programmable Dataflow Accelerators
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11132728openalex-snapshot
BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation
inferred← citeshttps://doi.org/10.1145/3620665.3640387openalex-snapshot
FPGA Technology Mapping Using Sketch-Guided Program Synthesis
inferred← citeshttps://doi.org/10.1145/3622781.3674170openalex-snapshot
Control Logic Synthesis: Drawing the Rest of the OWL
inferred← citeshttps://doi.org/10.1145/3622781.3674184openalex-snapshot
Don't Repeat Yourself! Coarse-Grained Circuit Deduplication to Accelerate RTL Simulation
inferred← citeshttps://doi.org/10.1145/3632860openalex-snapshot
Programming-by-Demonstration for Long-Horizon Robot Tasks
inferred← citeshttps://doi.org/10.1145/3669940.3707237openalex-snapshot
Automatic Tracing in Task-Based Runtime Systems
inferred← citeshttps://doi.org/10.1145/3808294openalex-snapshot
Fungible Memories for Automated Technology Mapping and Retargeting
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Exploiting Sophisticated Static Analysis for Verilog
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Incremental Program Synthesis from Event Logs
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