On the public citation graph

Compound Memory Models

https://doi.org/10.1145/3591267
0 signed · 32 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-03359-9_27openalex-snapshot
A Better x86 Memory Model: x86-TSO
inferredcites →https://doi.org/10.1098/rsta.2015.0406openalex-snapshot
Compositional relaxed concurrency
inferredcites →https://doi.org/10.1109/hpca53966.2022.00061openalex-snapshot
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols
inferredcites →https://doi.org/10.1109/pact.2017.29openalex-snapshot
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility
inferredcites →https://doi.org/10.1109/tc.1979.1675439openalex-snapshot
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
inferredcites →https://doi.org/10.1145/1024393openalex-snapshot
Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
inferredcites →https://doi.org/10.1145/1785414.1785443openalex-snapshot
x86-TSO
inferredcites →https://doi.org/10.1145/1926385.1926394openalex-snapshot
Mathematizing C++ concurrency
inferredcites →https://doi.org/10.1145/2254064.2254102openalex-snapshot
Synchronising C/C++ and POWER
inferredcites →https://doi.org/10.1145/2627752openalex-snapshot
Herding Cats
inferredcites →https://doi.org/10.1145/3009837.3009839openalex-snapshot
Mixed-size concurrency: ARM, POWER, C/C++11, and SC
inferredcites →https://doi.org/10.1145/3009837.3009850openalex-snapshot
A promising semantics for relaxed-memory concurrency
inferredcites →https://doi.org/10.1145/3062341.3062352openalex-snapshot
Repairing sequential consistency in C/C++11
inferredcites →https://doi.org/10.1145/3290382openalex-snapshot
Bridging the gap between programming languages and hardware weak memory models
inferredcites →https://doi.org/10.1145/3290383openalex-snapshot
Grounding thin-air reads with event structures
inferredcites →https://doi.org/10.1145/3297858.3304043openalex-snapshot
A Formal Analysis of the NVIDIA PTX Memory Consistency Model
inferredcites →https://doi.org/10.1145/3458926openalex-snapshot
Armed Cats
inferredcites →https://doi.org/10.1145/3485497openalex-snapshot
The semantics of shared memory in Intel CPU/FPGA systems
inferredcites →https://doi.org/10.2200/s00962ed2v01y201910cac049openalex-snapshot
A Primer on Memory Consistency and Cache Coherence, Second Edition
inferredcites →https://doi.org/10.5281/zenodo.7711175openalex-snapshot
[PLDI'23] Compound Memory Models: Artifact
inferredcites →https://doi.org/10.5860/choice.44-2746openalex-snapshot
Software abstractions: logic, language and analysis

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-78750-8_5openalex-snapshot
Formalisation of a New Weak Semantics for AuDaLa
inferred← citeshttps://doi.org/10.1007/978-3-031-98682-6_17openalex-snapshot
$$\textsf{GPUMC}$$: A Stateless Model Checker for GPU Weak Memory Concurrency
inferred← citeshttps://doi.org/10.1007/978-3-032-26220-2_20openalex-snapshot
Reasoning over Relaxed Shared Memory Models: A Tutorial
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408469openalex-snapshot
C³: CXL Coherence Controllers for Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1145/3640537.3641565openalex-snapshot
UNIFICO: Thread Migration in Heterogeneous-ISA CPUs without State Transformation
inferred← citeshttps://doi.org/10.1145/3676641.3715999openalex-snapshot
Formalising CXL Cache Coherence
inferred← citeshttps://doi.org/10.1145/3689749openalex-snapshot
Extending the C/C++ Memory Model with Inline Assembly
inferred← citeshttps://doi.org/10.1145/3695053.3731074openalex-snapshot
CORD: Low-Latency, Bandwidth-Efficient and Scalable Release Consistency via Directory Ordering
inferred← citeshttps://doi.org/10.1145/3779031.3779106openalex-snapshot
Towards Composable Proofs of Cache Coherence Protocols
inferred← citeshttps://doi.org/10.1145/3779212.3790245openalex-snapshot
vCXLGen: Automated Synthesis and Verification of CXL Bridges for Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1145/3808350openalex-snapshot
A Formally Verified Foundation for Compositional Heterogeneous Coherence
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.