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Bridging the gap between programming languages and hardware weak memory models
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-48989-6_29openalex-snapshot
Explaining Relaxed Memory Models with Program Transformations
inferredcites →https://doi.org/10.1007/978-3-642-03359-9_27openalex-snapshot
A Better x86 Memory Model: x86-TSO
inferredcites →https://doi.org/10.1109/cgo.2017.7863732openalex-snapshot
Formalizing the concurrency semantics of an LLVM fragment
inferredcites →https://doi.org/10.1109/isca.2018.00021openalex-snapshot
Constructing a Weak Memory Model
inferredcites →https://doi.org/10.1145/1538788.1538814openalex-snapshot
Formal verification of a realistic compiler
inferredcites →https://doi.org/10.1145/1926385.1926394openalex-snapshot
Mathematizing C++ concurrency
inferredcites →https://doi.org/10.1145/2103656.2103717openalex-snapshot
Clarifying and compiling C/C++ concurrency
inferredcites →https://doi.org/10.1145/2676726.2676995openalex-snapshot
Common Compiler Optimisations are Invalid in the C11 Memory Model and what we can do about it
inferredcites →https://doi.org/10.1145/2837614.2837615openalex-snapshot
Modelling the ARMv8 architecture, operationally: concurrency and ISA
inferredcites →https://doi.org/10.1145/2837614.2837616openalex-snapshot
A concurrency semantics for relaxed atomics that permits optimisation and avoids thin-air executions
inferredcites →https://doi.org/10.1145/2837614.2837643openalex-snapshot
Taming release-acquire consistency
inferredcites →https://doi.org/10.1145/2933575.2934536openalex-snapshot
On Thin Air Reads Towards an Event Structures Model of Relaxed Memory
inferredcites →https://doi.org/10.1145/3009837.3009838openalex-snapshot
Automatically comparing memory consistency models
inferredcites →https://doi.org/10.1145/3009837.3009839openalex-snapshot
Mixed-size concurrency: ARM, POWER, C/C++11, and SC
inferredcites →https://doi.org/10.1145/3009837.3009850openalex-snapshot
A promising semantics for relaxed-memory concurrency
inferredcites →https://doi.org/10.1145/3062341.3062352openalex-snapshot
Repairing sequential consistency in C/C++11
inferredcites →https://doi.org/10.1145/3158106openalex-snapshot
Transactions in relaxed memory architectures
inferredcites →https://doi.org/10.1145/3158107openalex-snapshot
Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8
inferredcites →https://doi.org/10.1145/3173162.3177156openalex-snapshot
Frightening Small Children and Disconcerting Grown-ups
inferredcites →https://doi.org/10.1145/3192366.3192373openalex-snapshot
The semantics of transactions and weak memory in x86, Power, ARM, and C++
inferredcites →https://doi.org/10.1145/3192366.3192421openalex-snapshot
Bounding data races in space and time
inferredcites →https://doi.org/10.1145/3290383openalex-snapshot
Grounding thin-air reads with event structures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-44914-8_22openalex-snapshot
Modular Relaxed Dependencies in Weak Memory Concurrency
inferred← citeshttps://doi.org/10.1007/978-3-030-81685-8_20openalex-snapshot
GenMC: A Model Checker for Weak Memory Models
inferred← citeshttps://doi.org/10.1007/978-3-030-90870-6_13openalex-snapshot
Owicki-Gries Reasoning for C11 Programs with Relaxed Dependencies
inferred← citeshttps://doi.org/10.1007/978-3-030-91014-3_16openalex-snapshot
BAM: Efficient Model Checking for Barriers
inferred← citeshttps://doi.org/10.1007/978-3-030-91014-3_17openalex-snapshot
Verifying and Optimizing the HMCS Lock for Arm Servers
inferred← citeshttps://doi.org/10.1007/978-3-031-57249-4_4openalex-snapshot
Enhancing GenMC’s Usability and Performance
inferred← citeshttps://doi.org/10.1007/978-3-031-71162-6_23openalex-snapshot
Accurate Static Data Race Detection for C
inferred← citeshttps://doi.org/10.1007/978-3-031-91118-7_3openalex-snapshot
Sufficient Conditions for Robustness of RDMA Programs
inferred← citeshttps://doi.org/10.1007/978-3-031-98668-0_18openalex-snapshot
Structural Operational Semantics for Functional and Security Verification of Pipelined Processors
inferred← citeshttps://doi.org/10.1007/978-3-031-98682-6_17openalex-snapshot
$$\textsf{GPUMC}$$: A Stateless Model Checker for GPU Weak Memory Concurrency
inferred← citeshttps://doi.org/10.1007/978-3-032-32526-6_10openalex-snapshot
Burrow: A Proof Framework for Weak Memory
inferred← citeshttps://doi.org/10.1017/s0956796821000162openalex-snapshot
Verified secure compilation for mixed-sensitivity concurrent programs
inferred← citeshttps://doi.org/10.1109/cgo57630.2024.10444836openalex-snapshot
Compiler Testing with Relaxed Memory Models
inferred← citeshttps://doi.org/10.1109/tase52547.2021.00023openalex-snapshot
Dynamic Verification of C11 Concurrency over Multi Copy Atomics
inferred← citeshttps://doi.org/10.1109/tc.2025.3595078openalex-snapshot
Parallelization Strategies for DeepMD-Kit Using OpenMP: Enhancing Efficiency in Machine Learning-Based Molecular Simulations
inferred← citeshttps://doi.org/10.1134/s0361768821060050openalex-snapshot
A Survey of Programming Language Memory Models
inferred← citeshttps://doi.org/10.1145/3290383openalex-snapshot
Grounding thin-air reads with event structures
inferred← citeshttps://doi.org/10.1145/3314221.3314595openalex-snapshot
Towards certified separate compilation for concurrent programs
inferred← citeshttps://doi.org/10.1145/3360561openalex-snapshot
Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models
inferred← citeshttps://doi.org/10.1145/3385412.3385973openalex-snapshot
Repairing and mechanising the JavaScript relaxed memory model
inferred← citeshttps://doi.org/10.1145/3385412.3386010openalex-snapshot
Promising 2.0: global optimizations in relaxed memory concurrency
inferred← citeshttps://doi.org/10.1145/3428262openalex-snapshot
Pomsets with preconditions: a simple model of relaxed memory
inferred← citeshttps://doi.org/10.1145/3434285openalex-snapshot
Verifying observational robustness against a c11-style memory model
inferred← citeshttps://doi.org/10.1145/3434337openalex-snapshot
Deciding reachability under persistent x86-TSO
inferred← citeshttps://doi.org/10.1145/3445814.3446748openalex-snapshot
VSync: push-button verification and optimization for synchronization primitives on weak memory models
inferred← citeshttps://doi.org/10.1145/3453483.3454082openalex-snapshot
Modular data-race-freedom guarantees in the promising semantics
inferred← citeshttps://doi.org/10.1145/3485541openalex-snapshot
The reads-from equivalence for the TSO and PSO memory models
inferred← citeshttps://doi.org/10.1145/3498683openalex-snapshot
Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores
inferred← citeshttps://doi.org/10.1145/3519939.3523718openalex-snapshot
Sequential reasoning for optimizing compilers under weak memory concurrency
inferred← citeshttps://doi.org/10.1145/3519939.3523719openalex-snapshot
Lasagne: a static binary translator for weak memory model architectures
inferred← citeshttps://doi.org/10.1145/3519939.3523734openalex-snapshot
Verifying optimizations of concurrent programs in the promising semantics
inferred← citeshttps://doi.org/10.1145/3563315openalex-snapshot
Model checking for a multi-execution memory model
inferred← citeshttps://doi.org/10.1145/3567955.3567962openalex-snapshot
Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures
inferred← citeshttps://doi.org/10.1145/3571212openalex-snapshot
Kater: Automating Weak Memory Model Metatheory and Consistency Checking
inferred← citeshttps://doi.org/10.1145/3580285openalex-snapshot
Mechanised Operational Reasoning for C11 Programs with Relaxed Dependencies
inferred← citeshttps://doi.org/10.1145/3591297openalex-snapshot
Putting Weak Memory in Order via a Promising Intermediate Representation
inferred← citeshttps://doi.org/10.1145/3650212.3685549openalex-snapshot
Robustness against the C/C++11 Memory Model
inferred← citeshttps://doi.org/10.1145/3656019.3676944openalex-snapshot
Toast: A Heterogeneous Memory Management System
inferred← citeshttps://doi.org/10.1145/3689749openalex-snapshot
Extending the C/C++ Memory Model with Inline Assembly
inferred← citeshttps://doi.org/10.1145/3689781openalex-snapshot
Semantics of Remote Direct Memory Access: Operational and Declarative Models of RDMA on TSO Architectures
inferred← citeshttps://doi.org/10.1145/3703595.3705890openalex-snapshot
Monadic Interpreters for Concurrent Memory Models
inferred← citeshttps://doi.org/10.1145/3704908openalex-snapshot
Relaxed Memory Concurrency Re-executed
inferred← citeshttps://doi.org/10.1145/3721089openalex-snapshot
Symbolic MRD: Dynamic Memory, Undefined Behaviour, and Extrinsic Choice
inferred← citeshttps://doi.org/10.1145/3721143openalex-snapshot
Memory Consistency and Program Transformations
inferred← citeshttps://doi.org/10.1145/3776650openalex-snapshot
ArchSem: Reusable Rigorous Semantics of Relaxed Architectures
inferred← citeshttps://doi.org/10.1145/3776687openalex-snapshot
Recurrence Sets for Proving Fair Non-termination under Axiomatic Memory Consistency Models
inferred← citeshttps://doi.org/10.1145/3779212.3790127openalex-snapshot
Arancini: A Hybrid Binary Translator for Weak Memory Model Architectures
inferred← citeshttps://doi.org/10.1145/3798208openalex-snapshot
RAT-CAT-SAT: Model Checking Memory Consistency Models
inferred← citeshttps://doi.org/10.1145/3839465openalex-snapshot
A Formal Account of the Wasm 3.0 Concurrency Model
inferred← citeshttps://doi.org/10.21275/sr231116134821openalex-snapshot
Bridging the Gap between Event-Based Programming and Functional Programming
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