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FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism

https://doi.org/10.1145/3614224
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/asap52443.2021.00029openalex-snapshot
OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays
inferredcites →https://doi.org/10.1109/asap52443.2021.00030openalex-snapshot
CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper)
inferredcites →https://doi.org/10.1109/asap54787.2022.00017openalex-snapshot
A “New Ara” for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
inferredcites →https://doi.org/10.1109/dsd53832.2021.00015openalex-snapshot
An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems
inferredcites →https://doi.org/10.1109/fpl57034.2022.00021openalex-snapshot
TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework
inferredcites →https://doi.org/10.1109/hpca53966.2022.00030openalex-snapshot
DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs
inferredcites →https://doi.org/10.1109/iiswc.2014.6983050openalex-snapshot
MachSuite: Benchmarks for accelerator design and customized architectures
inferredcites →https://doi.org/10.1109/isca52012.2021.00084openalex-snapshot
Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture
inferredcites →https://doi.org/10.1109/jssc.2019.2952839openalex-snapshot
A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection
inferredcites →https://doi.org/10.1109/mcse.2021.3057203openalex-snapshot
Accelerating Scientific Applications With SambaNova Reconfigurable Dataflow Architecture
inferredcites →https://doi.org/10.1109/micro56248.2022.00018openalex-snapshot
OverGen: Improving FPGA Usability through Domain-specific Overlay Generation
inferredcites →https://doi.org/10.1109/mm.2020.2996616openalex-snapshot
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
inferredcites →https://doi.org/10.1109/tcad.2017.2682645openalex-snapshot
Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures
inferredcites →https://doi.org/10.1109/tcad.2021.3058313openalex-snapshot
ChordMap: Automated Mapping of Streaming Applications Onto CGRA
inferredcites →https://doi.org/10.1109/tcad.2021.3123178openalex-snapshot
Specializing CGRAs for Light-Weight Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/tvlsi.2020.2972392openalex-snapshot
PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping
inferredcites →https://doi.org/10.1145/1669112.1669160openalex-snapshot
Polymorphic pipeline array
inferredcites →https://doi.org/10.1145/3079856.3080256openalex-snapshot
Plasticine
inferredcites →https://doi.org/10.1145/3489517.3530429openalex-snapshot
PANORAMA
inferredcites →https://doi.org/10.1145/3489517.3530454openalex-snapshot
Mixed-granularity parallel coarse-grained reconfigurable architecture
inferredcites →https://doi.org/10.1145/3503222.3507772openalex-snapshot
REVAMP: a systematic framework for heterogeneous CGRA realization
inferredcites →https://doi.org/10.1145/3534933openalex-snapshot
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
inferredcites →https://doi.org/10.4230/oasics.parma-ditam.2022.1openalex-snapshot
SO(DA)^2: End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk)

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/dac63849.2025.11132391openalex-snapshot
Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240863openalex-snapshot
DynVec: An End-to-End Framework for Efficient Vector-Dataflow Execution
inferred← citeshttps://doi.org/10.1109/iccpct70290.2026.11654917openalex-snapshot
Design of a 32-Bit RISC-V Processor with Dynamic Floating-Point ALU Switching
inferred← citeshttps://doi.org/10.1109/icfpt64416.2024.11113442openalex-snapshot
CGRA-HD: An Efficient Reconfigurable Accelerator for Hyperdimensional Computing: (PhD Forum Paper)
inferred← citeshttps://doi.org/10.1109/icfpt67023.2025.00034openalex-snapshot
Hacking the Pipeline: Enabling Fine-Grain Reconfigurable Acceleration within CPU Cores
inferred← citeshttps://doi.org/10.1109/iclad65226.2025.00031openalex-snapshot
HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design
inferred← citeshttps://doi.org/10.1109/ipdpsw71298.2026.00102openalex-snapshot
Control-Flow Execution on CGRAs: A Comprehensive Survey of Architectural and Compilation Techniques
inferred← citeshttps://doi.org/10.1109/iscait69154.2026.11477182openalex-snapshot
A RISC-V Heterogeneous SoC and Its Co-Scheduling Optimization Approach for Digital Signal Processing
inferred← citeshttps://doi.org/10.1109/mac64480.2025.11140495openalex-snapshot
Millimeter Wave Dielectric Resonator Antenna for 5G Communications with U-shaped ground cavity
inferred← citeshttps://doi.org/10.1109/tc.2025.3585345openalex-snapshot
COFFA: A Co -Design F ramework for F used-Grained Reconfigurable A rchitecture Towards Efficient Irregular Loop Handling
inferred← citeshttps://doi.org/10.1109/tcad.2025.3642732openalex-snapshot
Dependency-Aware Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring
inferred← citeshttps://doi.org/10.1109/tcad.2026.3653869openalex-snapshot
TransMap: Transformer-Enhanced Divide-and-Conquer Reinforcement Learning Framework for Efficient CGRA Compilation
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3697086openalex-snapshot
Toward Efficient Edge AI With Heterogeneous Computing and Multilevel Optimization
inferred← citeshttps://doi.org/10.1145/3658617.3697544openalex-snapshot
Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring
inferred← citeshttps://doi.org/10.1145/3658617.3697563openalex-snapshot
HDCC: A Hierarchical Dataflow-Oriented CGRA Compiler for Complex Applications
inferred← citeshttps://doi.org/10.1145/3733721openalex-snapshot
DVHetero: A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA
inferred← citeshttps://doi.org/10.1145/3766063openalex-snapshot
MoDAF: A Multi-objective Divide-and-Conquer Parameter Tuning Framework for CGRAs
inferred← citeshttps://doi.org/10.1145/3816253openalex-snapshot
A Configurable RISC-V Co-Processor with Instruction-Controlled Stream-Based Accelerators
inferred← citeshttps://doi.org/10.23919/date58400.2024.10546646openalex-snapshot
An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture
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