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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4020-6505-7_6openalex-snapshot
ADRES & DRESC: Architecture and Compiler for Coarse-Grain Reconfigurable Processors
inferredcites →https://doi.org/10.1007/978-3-030-53288-8_19openalex-snapshot
fault: A Python Embedded Domain-Specific Language for Metaprogramming Portable Hardware Verification Components
inferredcites →https://doi.org/10.1007/978-3-540-27764-4_11openalex-snapshot
An Algebra of Scans
inferredcites →https://doi.org/10.1007/978-94-015-7744-1_2openalex-snapshot
Simulated annealing
inferredcites →https://doi.org/10.1007/s10617-012-9096-8openalex-snapshot
An overview of today’s high-level synthesis tools
inferredcites →https://doi.org/10.1109/asap.2017.7995277openalex-snapshot
CGRA-ME: A unified framework for CGRA modelling and exploration
inferredcites →https://doi.org/10.1109/cgo.2019.8661185openalex-snapshot
Tensor Algebra Compilation with Workspaces
inferredcites →https://doi.org/10.1109/comst.2004.5342296openalex-snapshot
A survey of topologies and performance measures for large-scale networks
inferredcites →https://doi.org/10.1109/dac18072.2020.9218553openalex-snapshot
Creating an Agile Hardware Design Flow
inferredcites →https://doi.org/10.1109/fccm51124.2021.00030openalex-snapshot
Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs
inferredcites →https://doi.org/10.1109/hpca51647.2021.00042openalex-snapshot
Ultra-Elastic CGRAs for Irregular Loop Specialization
inferredcites →https://doi.org/10.1109/hpcc.and.euc.2013.154openalex-snapshot
An Efficient Graph Isomorphism Algorithm Based on Canonical Labeling and Its Parallel Implementation on GPU
inferredcites →https://doi.org/10.1109/iccad.2014.7001421openalex-snapshot
Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942127openalex-snapshot
MAGNet: A Modular Accelerator Generator for Neural Networks
inferredcites →https://doi.org/10.1109/micro.2016.7783720openalex-snapshot
From high-level deep neural models to FPGAs
inferredcites →https://doi.org/10.1109/micro.2016.7783755openalex-snapshot
Evaluating programmable architectures for imaging and vision applications
inferredcites →https://doi.org/10.1109/mm.2012.51openalex-snapshot
DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing
inferredcites →https://doi.org/10.1109/mm.2020.2996616openalex-snapshot
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
inferredcites →https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830509openalex-snapshot
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
inferredcites →https://doi.org/10.1145/1055137.1055187openalex-snapshot
APlace
inferredcites →https://doi.org/10.1145/1950413.1950423openalex-snapshot
LegUp
inferredcites →https://doi.org/10.1145/2435264.2435271openalex-snapshot
Improving high level synthesis optimization opportunity through polyhedral transformations
inferredcites →https://doi.org/10.1145/2491956.2462176openalex-snapshot
Halide
inferredcites →https://doi.org/10.1145/2601097.2601174openalex-snapshot
Darkroom
inferredcites →https://doi.org/10.1145/2647868.2654889openalex-snapshot
Caffe
inferredcites →https://doi.org/10.1145/2656075.2656081openalex-snapshot
Code generation from a domain-specific language for C-based HLS of hardware accelerators
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/275107.275134openalex-snapshot
A fast routability-driven router for FPGAs
inferredcites →https://doi.org/10.1145/2897824.2925892openalex-snapshot
Rigel
inferredcites →https://doi.org/10.1145/2897824.2925952openalex-snapshot
Automatically scheduling halide image processing pipelines
inferredcites →https://doi.org/10.1145/2967938.2967969openalex-snapshot
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs
inferredcites →https://doi.org/10.1145/3079856.3080256openalex-snapshot
Plasticine
inferredcites →https://doi.org/10.1145/3107953openalex-snapshot
Programming Heterogeneous Systems from an Image Processing DSL
inferredcites →https://doi.org/10.1145/3133901openalex-snapshot
The tensor algebra compiler
inferredcites →https://doi.org/10.1145/3140659.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3192366.3192379openalex-snapshot
Spatial: a language and compiler for application accelerators
inferredcites →https://doi.org/10.1145/3229762.3229766openalex-snapshot
Leveraging the VTA-TVM Hardware-Software Stack for FPGA Acceleration of 8-bit ResNet-18 Inference
inferredcites →https://doi.org/10.1145/3240765.3240801openalex-snapshot
DNNBuilder
inferredcites →https://doi.org/10.1145/3240765.3240850openalex-snapshot
SODA
inferredcites →https://doi.org/10.1145/3289602.3293910openalex-snapshot
HeteroCL
inferredcites →https://doi.org/10.1145/3296957.3173176openalex-snapshot
MAERI
inferredcites →https://doi.org/10.1145/3373087.3375306openalex-snapshot
AutoDNNchip
inferredcites →https://doi.org/10.1145/3373087.3375320openalex-snapshot
HeteroHalide
inferredcites →https://doi.org/10.1145/3395633openalex-snapshot
Replication Package for Article: Type-Directed Scheduling of Streaming Accelerators
inferredcites →https://doi.org/10.1145/3489517.3530633openalex-snapshot
mflowgen
inferredcites →https://doi.org/10.1145/504709.504710openalex-snapshot
Operator strength reduction
inferredcites →https://doi.org/10.14288/1.0065088openalex-snapshot
FPGA routing structures : a novel switch block and depopulated interconnect matrix architectures
inferredcites →https://doi.org/10.23919/date48585.2020.9116477openalex-snapshot
A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs
inferredcites →https://doi.org/10.34727/2021/isbn.978-3-85448-046-4_19openalex-snapshot
Automating System Configuration
inferredcites →https://doi.org/10.4230/lipics.snapl.2019.7openalex-snapshot
A Golden Age of Hardware Description Languages: Applying Programming Language Techniques to Improve Design Productivity
inferredcites →https://doi.org/10.48550/arxiv.2105.12858openalex-snapshot
Compiling Halide Programs to Push-Memory Accelerators

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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ImageMap: Enabling Efficient Mapping from Image Processing DSL to CGRA
inferred← citeshttps://doi.org/10.1109/asap71856.2026.00024openalex-snapshot
Zero-Overhead Loop Control for Tightly Coupled Processor Arrays (TCPAS)
inferred← citeshttps://doi.org/10.1109/asp-dac58780.2024.10473891openalex-snapshot
A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated Operators
inferred← citeshttps://doi.org/10.1109/fccm57271.2023.00054openalex-snapshot
PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design
inferred← citeshttps://doi.org/10.1109/fpl64840.2024.00037openalex-snapshot
CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00088openalex-snapshot
EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform
inferred← citeshttps://doi.org/10.1109/icfpt56656.2022.9974201openalex-snapshot
Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration
inferred← citeshttps://doi.org/10.1109/iclad65226.2025.00031openalex-snapshot
HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design
inferred← citeshttps://doi.org/10.1109/icmmts62835.2025.10926028openalex-snapshot
Towards Computing a Real-Time THz Material Map
inferred← citeshttps://doi.org/10.1109/ipdpsw71298.2026.00054openalex-snapshot
Configurable Architecture Design Automation (CADA) - Enabling Efficient, Dynamically Reconfigurable Systems
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00184openalex-snapshot
DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays
inferred← citeshttps://doi.org/10.1109/iscas46773.2023.10182052openalex-snapshot
An Open-Source $4 \times 8$ Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow
inferred← citeshttps://doi.org/10.1109/islped65674.2025.11261784openalex-snapshot
An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems
inferred← citeshttps://doi.org/10.1109/jssc.2023.3313116openalex-snapshot
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
inferred← citeshttps://doi.org/10.1109/jssc.2025.3604724openalex-snapshot
Onyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications
inferred← citeshttps://doi.org/10.1109/lssc.2025.3613245openalex-snapshot
Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00018openalex-snapshot
OverGen: Improving FPGA Usability through Domain-specific Overlay Generation
inferred← citeshttps://doi.org/10.1109/tc.2025.3585345openalex-snapshot
COFFA: A Co -Design F ramework for F used-Grained Reconfigurable A rchitecture Towards Efficient Irregular Loop Handling
inferred← citeshttps://doi.org/10.1109/tcad.2024.3390542openalex-snapshot
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
inferred← citeshttps://doi.org/10.1109/tcad.2026.3653869openalex-snapshot
TransMap: Transformer-Enhanced Divide-and-Conquer Reinforcement Learning Framework for Efficient CGRA Compilation
inferred← citeshttps://doi.org/10.1109/tpds.2025.3561145openalex-snapshot
Raccoon: Lightweight Support for Comprehensive Control Flows in Reconfigurable Spatial Architectures
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3344536openalex-snapshot
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3697086openalex-snapshot
Toward Efficient Edge AI With Heterogeneous Computing and Multilevel Optimization
inferred← citeshttps://doi.org/10.1145/3577193.3593707openalex-snapshot
Towards a Unified Implementation of GEMM in BLIS
inferred← citeshttps://doi.org/10.1145/3582016.3582070openalex-snapshot
APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis
inferred← citeshttps://doi.org/10.1145/3605507.3610632openalex-snapshot
Building First-Order Energy Modeling Intuition in Computer Architecture Lectures
inferred← citeshttps://doi.org/10.1145/3614224openalex-snapshot
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism
inferred← citeshttps://doi.org/10.1145/3656176openalex-snapshot
HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration
inferred← citeshttps://doi.org/10.1145/3656642openalex-snapshot
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA
inferred← citeshttps://doi.org/10.1145/3695053.3731004openalex-snapshot
Assassyn: A Unified Abstraction for Architectural Simulation and Implementation
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Reconfigurable Stream Network Architecture
inferred← citeshttps://doi.org/10.1145/3708821.3736216openalex-snapshot
Telescope: Top-Down Hierarchical Pre-silicon Side-channel Leakage Assessment in System-on-Chip Design
inferred← citeshttps://doi.org/10.1145/3721888.3722095openalex-snapshot
Compiler-aware AI Hardware Design for Edge Devices
inferred← citeshttps://doi.org/10.1145/3725843.3756075openalex-snapshot
TAIDL: Tensor Accelerator ISA Definition Language with Auto-generation of Scalable Test Oracles
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RIMMS: Runtime Integrated Memory Management System for Heterogeneous Computing
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MoDAF: A Multi-objective Divide-and-Conquer Parameter Tuning Framework for CGRAs
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AHCA: Agile Design Framework for Hashcat Acceleration Based on FPGA
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Neura: A Unified Framework for Hierarchical and Adaptive CGRAs
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Technology trends in computing hardware and their impacts on high-performance scientific computing Part I: General-purpose processors and hardware accelerators
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MC-CGRA: A Memory-Computation Coordinated CGRA Framework for Stream Processing
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