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Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors

https://doi.org/10.1145/3624062.3624229
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/0-387-27705-6_9openalex-snapshot
Computer Architecture
inferredcites →https://doi.org/10.1007/978-3-540-77304-7_13openalex-snapshot
High Performance Computing
inferredcites →https://doi.org/10.1016/c2013-0-08305-3openalex-snapshot
Computer Organization and Design
inferredcites →https://doi.org/10.1109/cvpr.2016.90openalex-snapshot
Deep Residual Learning for Image Recognition
inferredcites →https://doi.org/10.1109/hcs49909.2020.9220630openalex-snapshot
Xuantie-910: Innovating Cloud and Edge Computing by RISC-V
inferredcites →https://doi.org/10.1109/isca45697.2020.00016openalex-snapshot
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product
inferredcites →https://doi.org/10.1109/jproc.2017.2761740openalex-snapshot
Efficient Processing of Deep Neural Networks: A Tutorial and Survey
inferredcites →https://doi.org/10.1109/meco58584.2023.10154913openalex-snapshot
Towards a RISC-V Open Platform for Next-generation Automotive ECUs
inferredcites →https://doi.org/10.1137/1.9781611971446openalex-snapshot
Applied Numerical Linear Algebra
inferredcites →https://doi.org/10.1145/1356052.1356053openalex-snapshot
Anatomy of high-performance matrix multiplication
inferredcites →https://doi.org/10.1145/2755561openalex-snapshot
The BLIS Framework
inferredcites →https://doi.org/10.1145/2764454openalex-snapshot
BLIS: A Framework for Rapidly Instantiating BLAS Functionality
inferredcites →https://doi.org/10.1145/2925987openalex-snapshot
Analytical Modeling Is Enough for High-Performance BLIS
inferredcites →https://doi.org/10.1145/77626.79170openalex-snapshot
A set of level 3 basic linear algebra subprograms
inferredcites →https://doi.org/10.2514/1.i010735openalex-snapshot
Leveraging the Openness and Modularity of RISC-V in Space

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.2139/ssrn.4676008openalex-extracted
inferred← citeshttps://doi.org/10.1007/978-3-031-73716-9_23openalex-snapshot
Performance Analysis of BERT on RISC-V Processors with SIMD Units
inferred← citeshttps://doi.org/10.1007/978-3-032-07612-0_33openalex-snapshot
Generation of Mixed-Precision Kernels for Quantized Transformer Encoders with Exo
inferred← citeshttps://doi.org/10.1007/978-3-032-07612-0_41openalex-snapshot
Evaluation of RVV-Enabled COTS Platforms with Matrix Multiplication and Exo
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103186openalex-snapshot
Parallel GEMM-based convolutions for deep learning on multicore ARM and RISC-V architectures
inferred← citeshttps://doi.org/10.1109/cscwd68734.2026.11582297openalex-snapshot
A Human-Machine Collaborative Code Translator from ARM NEON to RISC-V Vector
inferred← citeshttps://doi.org/10.1109/ipdps65963.2026.00093openalex-snapshot
Just-in-Time Convolution and GEMM Code Generation for SIMD Architectures
inferred← citeshttps://doi.org/10.1109/jiot.2025.3613691openalex-snapshot
A Survey of AI Inference Technologies for On-Device Systems
inferred← citeshttps://doi.org/10.1109/pdp66500.2025.00013openalex-snapshot
Portable, High Performance Matrix Multiplication Micro-Kernels for RISC-V with ExO
inferred← citeshttps://doi.org/10.1145/3725843.3756059openalex-snapshot
Titan-I: An Open-Source, High Performance RISC-V Vector Core
inferred← citeshttps://doi.org/10.1145/3774895.3815548openalex-snapshot
The RISC-V VecR extension: Adding internal registers to RVV
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