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Timing Side-channel Attacks and Countermeasures in CPU Microarchitectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4842-6586-4_21openalex-snapshot
Brute Force and Buffer Overflow Attacks
inferredcites →https://doi.org/10.1007/978-3-319-45719-2_6openalex-snapshot
CloudRadar: A Real-Time Side-Channel Attack Detection System in Clouds
inferredcites →https://doi.org/10.1007/s10617-008-9018-yopenalex-snapshot
Non deterministic caches: a simple and effective defense against side channel attacks
inferredcites →https://doi.org/10.1007/s10766-018-0611-9openalex-snapshot
MemJam: A False Dependency Attack Against Constant-Time Crypto Implementations
inferredcites →https://doi.org/10.1007/s13389-016-0141-6openalex-snapshot
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware
inferredcites →https://doi.org/10.1007/s13389-017-0152-yopenalex-snapshot
CacheBleed: a timing attack on OpenSSL constant-time RSA
inferredcites →https://doi.org/10.1109/eurosp.2019.00020openalex-snapshot
SgxPectre: Stealing Intel Secrets from SGX Enclaves Via Speculative Execution
inferredcites →https://doi.org/10.1109/mahc.2015.27openalex-snapshot
The Birth and Death of the Orange Book
inferredcites →https://doi.org/10.1109/tc.2019.2958611openalex-snapshot
Branch Prediction Attack on Blinded Scalar Multiplication
inferredcites →https://doi.org/10.1109/tcad.2023.3291669openalex-snapshot
Mex+Sync: Software Covert Channels Exploiting Mutual Exclusion and Synchronization
inferredcites →https://doi.org/10.1109/tnet.2014.2304439openalex-snapshot
Whispers in the Hyper-Space: High-Bandwidth and Reliable Covert Channel Attacks Inside the Cloud
inferredcites →https://doi.org/10.1109/tse.2019.2953709openalex-snapshot
oo7: Low-Overhead Defense Against Spectre Attacks via Program Analysis
inferredcites →https://doi.org/10.1145/2775054.2694372openalex-snapshot
A Hardware Design Language for Timing-Sensitive Information-Flow Security
inferredcites →https://doi.org/10.1145/2870636openalex-snapshot
Understanding and Mitigating Covert Channels Through Branch Predictors
inferredcites →https://doi.org/10.1145/3023872openalex-snapshot
A Survey of Timing Channels and Countermeasures
inferredcites →https://doi.org/10.1145/3268935.3268940openalex-snapshot
Mitigating Branch-Shadowing Attacks on Intel SGX using Control Flow Randomization
inferredcites →https://doi.org/10.1145/3320269.3384746openalex-snapshot
Take A Way: Exploring the Security Implications of AMD's Cache Way Predictors
inferredcites →https://doi.org/10.1145/3338508.3359574openalex-snapshot
Adaptive Caches as a Defense Mechanism Against Cache Side-Channel Attacks
inferredcites →https://doi.org/10.1145/3394885.3431638openalex-snapshot
Micro-architectural Cache Side-Channel Attacks and Countermeasures
inferredcites →https://doi.org/10.1145/3442479openalex-snapshot
Survey of Transient Execution Attacks and Their Mitigations
inferredcites →https://doi.org/10.1145/3456629openalex-snapshot
A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks, and Defenses in Cryptography
inferredcites →https://doi.org/10.3390/electronics8091057openalex-snapshot
Model-Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification
inferredcites →https://doi.org/10.48550/arxiv.1802.03802openalex-snapshot
MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols
inferredcites →https://doi.org/10.48550/arxiv.1806.07480openalex-snapshot
LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels
inferredcites →https://doi.org/10.48550/arxiv.1807.03757openalex-snapshot
Speculative Buffer Overflows: Attacks and Defenses
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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inferred← citeshttps://doi.org/10.1088/1402-4896/ad6407openalex-snapshot
GFLE: a low-energy lightweight block cipher based on a variant of generalized Feistel structure
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inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133149openalex-snapshot
Data Oblivious CPU: Microarchitectural Side-channel Leakage-Resilient Processor
inferred← citeshttps://doi.org/10.1109/ddecs69233.2026.11521000openalex-snapshot
Assessing the Vulnerability of Open-Source RISC-V Processors to Transient Execution Attacks
inferred← citeshttps://doi.org/10.1109/eit68936.2026.11670380openalex-snapshot
Security in Asynchronous Circuits: A Review of Side-Channel Attacks and Hardware Trojan Threats
inferred← citeshttps://doi.org/10.1109/hpec62836.2024.10938520openalex-snapshot
IOS: A Low Cost Defense to Mitigate Meltdown and Spectre Like Attacks
inferred← citeshttps://doi.org/10.1109/i-smac61858.2024.10714585openalex-snapshot
Hybrid Compiler and Hardware Approach to Mitigate Side-Channel Vulnerabilities in Parallel GPU Architectures
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11241011openalex-snapshot
CacheGuardian: A Timing Side-Channel Resilient LLC Design
inferred← citeshttps://doi.org/10.1109/icimct.2025.00029openalex-snapshot
Hierarchical Bayesian Network-Based Research on Converged Security Assessment for IoT System
inferred← citeshttps://doi.org/10.1109/icscn67106.2025.11308479openalex-snapshot
GPU Side-Channel Attack Resilience: NIST 2.0 Risk Management and Governance Strategies Assessment
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SLCF: Security-Level-Aware Microarchitectural Cleaning for Efficient Time Protection
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SynAssert: Automated Synthesis of CSCA Leakage Patterns into Cost-Effective Security Assertions
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TmsNet: An Efficient Transformer Network Based on Multiscale Shift-Invariance Mechanism for Side-Channel Analysis
inferred← citeshttps://doi.org/10.1109/lcn67947.2026.11660789openalex-snapshot
Round Trip Time: A Benign Signal or an Indirect Window into Datacenter Workloads?
inferred← citeshttps://doi.org/10.1109/ojcoms.2025.3560034openalex-snapshot
A Survey on Privacy and Security in Distributed Cloud Computing: Exploring Federated Learning and Beyond
inferred← citeshttps://doi.org/10.1109/socc66126.2025.11235471openalex-snapshot
Constant-Time Modulo: A Secure Hardware Design Against Timing Attacks
inferred← citeshttps://doi.org/10.1109/sp61157.2025.00209openalex-snapshot
I know What You Sync: Covert and Side Channel Attacks on File Systems via syncfs
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3583792openalex-snapshot
InstPro: Provenance-Based Transient Execution Attack Detection and Investigation on Instruction Execution Traces
inferred← citeshttps://doi.org/10.1109/tifs.2024.3414255openalex-snapshot
Write+Sync: Software Cache Write Covert Channels Exploiting Memory-Disk Synchronization
inferred← citeshttps://doi.org/10.1109/tifs.2026.3707433openalex-snapshot
DISARM: Target Electronic Device Informed Mitigation of Software Runtime Side-Channel Vulnerabilities
inferred← citeshttps://doi.org/10.1109/tsmc.2025.3613057openalex-snapshot
A New Encryption Algorithm for Secure Aviation Communications
inferred← citeshttps://doi.org/10.1109/tvt.2025.3566034openalex-snapshot
Hybrid-Generative Diffusion Models for Attack-Oriented Twin Migration in Vehicular Metaverses
inferred← citeshttps://doi.org/10.1109/vcris68011.2025.11250556openalex-snapshot
Side-Channel Attack on XOR Operation in the First Round of AES Implementation on the STM32 Microcontroller Board
inferred← citeshttps://doi.org/10.1145/3676536.3676838openalex-snapshot
µLAM: A LLM-Powered Assistant for Real-Time Micro-architectural Attack Detection and Mitigation
inferred← citeshttps://doi.org/10.1145/3698364.3705349openalex-snapshot
Photonic Side-Channel Analyzer: Enabling Security-Aware Physical Design Methodology
inferred← citeshttps://doi.org/10.1145/3725843.3756136openalex-snapshot
Sonar: A Hardware Fuzzing Framework to Uncover Contention Side Channels in Processors
inferred← citeshttps://doi.org/10.1145/3742872.3757056openalex-snapshot
Special Sessions - Emerging Scope and Design Challenges for Approximate Computing: Optimizing Accuracy-PPA trade-offs and Beyond
inferred← citeshttps://doi.org/10.1145/3746467.3801495openalex-snapshot
NeuroSnitch: Exploiting Inter-Spike Interval Statistics for Timing Side-Channel Attacks on Noisy Neuromorphic Systems
inferred← citeshttps://doi.org/10.1145/3800949openalex-snapshot
Unleashing Cross-Domain Potential: Side-Channel Analysis with Autoencoder for Domain Adaptation
inferred← citeshttps://doi.org/10.1145/3830418.3843883openalex-snapshot
Sockeye: Bug-finding and proofs for platform configurations and hardware based on reference manuals
inferred← citeshttps://doi.org/10.14569/ijacsa.2024.0150674openalex-snapshot
Dynamic Shader Termination and Throttling for Side-Channel Security on GPUOwl
inferred← citeshttps://doi.org/10.2139/ssrn.6963913openalex-snapshot
Confidentiality and Practicality of Trusted Execution Environments for Cross-Organizational Multi-Model Consistency Checking
inferred← citeshttps://doi.org/10.3390/app14156699openalex-snapshot
A Survey of of Side-Channel Attacks and Mitigation for Processor Interconnects
inferred← citeshttps://doi.org/10.3390/e28030254openalex-snapshot
Spec-LAMP: Robust Spectre Attack Detection Under Web-Based LLM Workload via L1D Miss Pending Event
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To (US)Be or Not to (US)Be: Discovering Malicious USB Peripherals through Neural Network-Driven Power Analysis
inferred← citeshttps://doi.org/10.3390/electronics14071384openalex-snapshot
Evaluating Large Language Model Application Impacts on Evasive Spectre Attack Detection
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TrackRISC: An Implicit Attack Flow Model and Hardware Microarchitectural Mitigation for Speculative Cache-Based Covert Channels
inferred← citeshttps://doi.org/10.5772/intechopen.1015223openalex-snapshot
Perspective Chapter: Exploiting System Errors to Develop a Flexible and Reliable Covert Channel
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