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Understanding and Mitigating Covert Channels Through Branch Predictors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/j.1538-7305.1950.tb00463.xopenalex-snapshot
Error Detecting and Error Correcting Codes
inferredcites →https://doi.org/10.1007/11967668_15openalex-snapshot
Predicting Secret Keys Via Branch Prediction
inferredcites →https://doi.org/10.1109/acsac.2006.20openalex-snapshot
Covert and Side Channels Due to Processor Architecture
inferredcites →https://doi.org/10.1109/csf.2015.26openalex-snapshot
BitWhisper: Covert Signaling Channel between Air-Gapped Computers Using Thermal Manipulations
inferredcites →https://doi.org/10.1109/hpca.2014.6835931openalex-snapshot
A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks
inferredcites →https://doi.org/10.1109/hpca.2014.6835934openalex-snapshot
Timing channel protection for a shared memory controller
inferredcites →https://doi.org/10.1109/hpca.2015.7056069openalex-snapshot
Understanding contention-based channels and using them for defense
inferredcites →https://doi.org/10.1109/ispass.2001.990679openalex-snapshot
The effects of context switching on branch predictor performance
inferredcites →https://doi.org/10.1109/micro.2014.25openalex-snapshot
Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution
inferredcites →https://doi.org/10.1109/micro.2014.42openalex-snapshot
CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware
inferredcites →https://doi.org/10.1109/risp.1991.130767openalex-snapshot
An analysis of covert timing channels
inferredcites →https://doi.org/10.1109/risp.1992.213271openalex-snapshot
Lattice scheduling and covert channels
inferredcites →https://doi.org/10.1109/sp.2009.25openalex-snapshot
Native Client: A Sandbox for Portable, Untrusted x86 Native Code
inferredcites →https://doi.org/10.1109/sp.2011.31openalex-snapshot
HomeAlone: Co-residency Detection in the Cloud via Side-Channel Analysis
inferredcites →https://doi.org/10.1109/sp.2015.45openalex-snapshot
Controlled-Channel Attacks: Deterministic Side Channels for Untrusted Operating Systems
inferredcites →https://doi.org/10.1109/tcad.2014.2331332openalex-snapshot
Leveraging Gate-Level Properties to Identify Hardware Timing Channels
inferredcites →https://doi.org/10.1145/1229285.1266999openalex-snapshot
On the power of simple branch prediction analysis
inferredcites →https://doi.org/10.1145/1508244.1508258openalex-snapshot
Complete information flow tracking from the gates up
inferredcites →https://doi.org/10.1145/1653662.1653687openalex-snapshot
Hey, you, get off of my cloud
inferredcites →https://doi.org/10.1145/1866307.1866341openalex-snapshot
Predictive black-box mitigation of timing channels
inferredcites →https://doi.org/10.1145/232973.232975openalex-snapshot
Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches
inferredcites →https://doi.org/10.1145/232974.232975openalex-snapshot
Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches
inferredcites →https://doi.org/10.1145/2487726.2488368openalex-snapshot
Innovative instructions and software model for isolated execution
inferredcites →https://doi.org/10.1145/2768566.2768571openalex-snapshot
Covert channels through branch predictors
inferredcites →https://doi.org/10.1145/2842621openalex-snapshot
Rethinking Memory Permissions for Protection Against Cross-Layer Attacks
inferredcites →https://doi.org/10.21236/ada477386openalex-snapshot
A Guide to Understanding Covert Channel Analysis of Trusted Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-01760-5openalex-snapshot
Principles of Secure Processor Architecture Design
inferred← citeshttps://doi.org/10.1007/978-3-319-72598-7_19openalex-snapshot
Performance Attacks on Branch Predictors in Embedded Processors with SMT Support
inferred← citeshttps://doi.org/10.1007/978-3-319-93387-0_5openalex-snapshot
Drive-By Key-Extraction Cache Attacks from Portable Code
inferred← citeshttps://doi.org/10.1007/s10766-018-0608-4openalex-snapshot
Covert Timing Channels Exploiting Cache Coherence Hardware: Characterization and Defense
inferred← citeshttps://doi.org/10.1007/s11390-019-1979-8openalex-snapshot
An Efficient Approach for Mitigating Covert Storage Channel Attacks in Virtual Machines by the Anti-Detection Criterion
inferred← citeshttps://doi.org/10.1007/s11390-021-1189-zopenalex-snapshot
Improving Performance of Virtual Machine Covert Timing Channel Through Optimized Run-Length Encoding
inferred← citeshttps://doi.org/10.1007/s11390-021-1253-8openalex-snapshot
A Novel Probabilistic Saturating Counter Design for Secure Branch Predictor
inferred← citeshttps://doi.org/10.1007/s41635-018-0046-1openalex-snapshot
Survey of Microarchitectural Side and Covert Channels, Attacks, and Defenses
inferred← citeshttps://doi.org/10.1007/s41635-021-00115-3openalex-snapshot
A Survey on Cache Timing Channel Attacks for Multicore Processors
inferred← citeshttps://doi.org/10.1109/asp-dac52403.2022.9712481openalex-snapshot
Lightweight and Secure Branch Predictors against Spectre Attacks
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586178openalex-snapshot
A Lightweight Isolation Mechanism for Secure Branch Predictors
inferred← citeshttps://doi.org/10.1109/dsn53405.2022.00023openalex-snapshot
STBPU: A Reasonably Secure Branch Prediction Unit
inferred← citeshttps://doi.org/10.1109/eurosp57164.2023.00044openalex-snapshot
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations
inferred← citeshttps://doi.org/10.1109/hpca.2018.00024openalex-snapshot
Are Coherence Protocol States Vulnerable to Information Leakage?
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00020openalex-snapshot
A New Side-Channel Vulnerability on Modern Computers by Exploiting Electromagnetic Emanations from the Power Management Unit
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00033openalex-snapshot
HyBP: Hybrid Isolation-Randomization Secure Branch Predictor
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00013openalex-snapshot
GADGETSPINNER: A New Transient Execution Primitive Using the Loop Stream Detector
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00038openalex-snapshot
Modeling, Derivation, and Automated Analysis of Branch Predictor Security Vulnerabilities
inferred← citeshttps://doi.org/10.1109/hst.2019.8741033openalex-snapshot
A Fetching Tale: Covert Communication with the Hardware Prefetcher
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323658openalex-snapshot
BeKnight: Guarding Against Information Leakage in Speculatively Updated Branch Predictors
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00095openalex-snapshot
BranchSpec: Information Leakage Attacks Exploiting Speculative Branch Instruction Executions
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00080openalex-snapshot
Leaky Buddies: Cross-Component Covert Channels on Integrated CPU-GPU Systems
inferred← citeshttps://doi.org/10.1109/mdat.2021.3063359openalex-snapshot
Beyond the CPU: Side–Channel Attacks on GPUs
inferred← citeshttps://doi.org/10.1109/micro.2016.7783743openalex-snapshot
Jump over ASLR: Attacking branch predictors to bypass ASLR
inferred← citeshttps://doi.org/10.1109/pact.2019.00012openalex-snapshot
SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors
inferred← citeshttps://doi.org/10.1109/seed55351.2022.00023openalex-snapshot
Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing
inferred← citeshttps://doi.org/10.1109/sp.2019.00062openalex-snapshot
The 9 Lives of Bleichenbacher's CAT: New Cache ATtacks on TLS Implementations
inferred← citeshttps://doi.org/10.1109/sp46214.2022.9833794openalex-snapshot
MeshUp: Stateless Cache Side-channel Attack on CPU Mesh
inferred← citeshttps://doi.org/10.1109/sp46215.2023.10179309openalex-snapshot
Half&Half: Demystifying Intel’s Directional Branch Predictors for Fast, Secure Partitioned Execution
inferred← citeshttps://doi.org/10.1109/sp46215.2023.10179415openalex-snapshot
Half&Half: Demystifying Intel’s Directional Branch Predictors for Fast, Secure Partitioned Execution
inferred← citeshttps://doi.org/10.1109/sp54263.2024.00062openalex-snapshot
BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
inferred← citeshttps://doi.org/10.1109/sp54263.2024.00180openalex-snapshot
ConjunCT: Learning Inductive Invariants to Prove Unbounded Instruction Safety Against Microarchitectural Timing Attacks
inferred← citeshttps://doi.org/10.1109/sp63933.2026.00066openalex-snapshot
Transient Architectural Execution: From Weird Gates to Weird Programs
inferred← citeshttps://doi.org/10.1109/tc.2019.2958611openalex-snapshot
Branch Prediction Attack on Blinded Scalar Multiplication
inferred← citeshttps://doi.org/10.1109/tc.2021.3122830openalex-snapshot
Leaking Secrets through Modern Branch Predictor in the Speculative World
inferred← citeshttps://doi.org/10.1109/tcad.2023.3291669openalex-snapshot
Mex+Sync: Software Covert Channels Exploiting Mutual Exclusion and Synchronization
inferred← citeshttps://doi.org/10.1109/tdsc.2016.2596287openalex-snapshot
Flexible Hardware-Managed Isolated Execution: Architecture, Software Support and Applications
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3580445openalex-snapshot
Systematic Analysis of Moving Target Defenses for Branch Prediction Attacks
inferred← citeshttps://doi.org/10.1109/vlsid.2018.54openalex-snapshot
Online Detection and Reactive Countermeasure for Leakage from BPU Using TVLA
inferred← citeshttps://doi.org/10.1145/2976749.2978374openalex-snapshot
Covert Channels through Random Number Generator
inferred← citeshttps://doi.org/10.1145/3060403.3060417openalex-snapshot
Covert Timing Channels Exploiting Non-Uniform Memory Access based Architectures
inferred← citeshttps://doi.org/10.1145/3123939.3124538openalex-snapshot
Constructing and characterizing covert channels on GPGPUs
inferred← citeshttps://doi.org/10.1145/3156015openalex-snapshot
Utilizing Performance Counters for Compromising Public Key Ciphers
inferred← citeshttps://doi.org/10.1145/3265723.3265724openalex-snapshot
No Security Without Time Protection
inferred← citeshttps://doi.org/10.1145/3433210.3437517openalex-snapshot
Red Alert for Power Leakage: Exploiting Intel RAPL-Induced Side Channels
inferred← citeshttps://doi.org/10.1145/3442479openalex-snapshot
Survey of Transient Execution Attacks and Their Mitigations
inferred← citeshttps://doi.org/10.1145/3445814.3446708openalex-snapshot
Speculative interference attacks: breaking invisible speculation schemes
inferred← citeshttps://doi.org/10.1145/3534962openalex-snapshot
Cache-related Hardware Capabilities and Their Impact on Information Security
inferred← citeshttps://doi.org/10.1145/3544102openalex-snapshot
Microarchitectural Attacks in Heterogeneous Systems: A Survey
inferred← citeshttps://doi.org/10.1145/3613424.3614259openalex-snapshot
Uncore Encore: Covert Channels Exploiting Uncore Frequency Scaling
inferred← citeshttps://doi.org/10.1145/3634737.3637648openalex-snapshot
WebGPU-SPY: Finding Fingerprints in the Sandbox through GPU Cache Attacks
inferred← citeshttps://doi.org/10.1145/3645109openalex-snapshot
Timing Side-channel Attacks and Countermeasures in CPU Microarchitectures
inferred← citeshttps://doi.org/10.1145/3649329.3655895openalex-snapshot
Conjuring: Leaking Control Flow via Speculative Fetch Attacks
inferred← citeshttps://doi.org/10.1145/3734218openalex-snapshot
A Survey of Side-Channel Attacks on Branch Prediction Units
inferred← citeshttps://doi.org/10.14722/ndss.2018.23221openalex-snapshot
Microarchitectural Minefields: 4K-Aliasing Covert Channel and Multi-Tenant Detection in Iaas Clouds
inferred← citeshttps://doi.org/10.14722/ndss.2019.23409openalex-snapshot
ExSpectre: Hiding Malware in Speculative Execution
inferred← citeshttps://doi.org/10.2200/s00864ed1v01y201807cac045openalex-snapshot
Principles of Secure Processor Architecture Design
inferred← citeshttps://doi.org/10.3390/app14156699openalex-snapshot
A Survey of of Side-Channel Attacks and Mitigation for Processor Interconnects
inferred← citeshttps://doi.org/10.3390/electronics14091758openalex-snapshot
BranchCloak: Mitigating Side-Channel Attacks on Directional Branch Predictors
inferred← citeshttps://doi.org/10.3390/s22197354openalex-snapshot
Cross-World Covert Channel on ARM Trustzone through PMU
inferred← citeshttps://doi.org/10.3929/ethz-b-000526898openalex-snapshot
We know what you're doing! Application detection using thermal data
inferred← citeshttps://doi.org/10.48550/arxiv.1608.03431openalex-snapshot
DiskFiltration: Data Exfiltration from Speakerless Air-Gapped Computers via Covert Hard Drive Noise
inferred← citeshttps://doi.org/10.48550/arxiv.1810.05345openalex-snapshot
Time Protection: the Missing OS Abstraction
inferred← citeshttps://doi.org/10.48550/arxiv.2005.08183openalex-snapshot
A Lightweight Isolation Mechanism for Secure Branch Predictors
inferred← citeshttps://doi.org/10.48550/arxiv.2103.03443openalex-snapshot
Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical
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