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FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Order-N tight-binding molecular dynamics on parallel computers
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tpSpMV: A two-phase large-scale sparse matrix-vector multiplication kernel for manycore architectures
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2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)
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Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture
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Towards a Universal FPGA Matrix-Vector Multiplication Architecture
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Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory
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Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs
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2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)
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SkeletonGCN: A Simple Yet Effective Accelerator For GCN Training
inferredcites →https://doi.org/10.1109/fpl60245.2023.00029openalex-snapshot
Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach
inferredcites →https://doi.org/10.1109/fpl60245.2023.00039openalex-snapshot
Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks
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2023 IEEE Guwahati Subsection Conference (GCON)
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ReMCOO: An Efficient Representation of Sparse Matrix-Vector Multiplication
inferredcites →https://doi.org/10.1109/hpca.2018.00067openalex-snapshot
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator
inferredcites →https://doi.org/10.1109/hpca47549.2020.00030openalex-snapshot
SpArch: Efficient Architecture for Sparse Matrix Multiplication
inferredcites →https://doi.org/10.1109/hpca51647.2021.00017openalex-snapshot
SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs
inferredcites →https://doi.org/10.1109/hpca56546.2023.10071015openalex-snapshot
FlowGNN: A Dataflow Architecture for Real-Time Workload-Agnostic Graph Neural Network Inference
inferredcites →https://doi.org/10.1109/hpcc-dss-smartcity-dependsys57074.2022.00171openalex-snapshot
A High-performance SpMV Accelerator on HBM-equipped FPGAs
inferredcites →https://doi.org/10.1109/hpec43672.2018openalex-snapshot
2018 IEEE High Performance extreme Computing Conference (HPEC)
inferredcites →https://doi.org/10.1109/iccad51958.2021openalex-snapshot
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/iccad51958.2021.9643453openalex-snapshot
Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs
inferredcites →https://doi.org/10.1109/iccad51958.2021.9643582openalex-snapshot
GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs
inferredcites →https://doi.org/10.1109/ipdps.2013.43openalex-snapshot
Improving the Performance of the Symmetric Sparse Matrix-Vector Multiplication in Multicore
inferredcites →https://doi.org/10.1109/ipdps53621.2022openalex-snapshot
2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
inferredcites →https://doi.org/10.1109/ipdps54959.2023.00032openalex-snapshot
Dynasparse: Accelerating GNN Inference through Dynamic Sparsity Exploitation
inferredcites →https://doi.org/10.1109/ipdpsw.2015.75openalex-snapshot
Parallel Triangle Counting and Enumeration Using Matrix Algebra
inferredcites →https://doi.org/10.1109/isca19853.2012openalex-snapshot
2012 39th Annual International Symposium on Computer Architecture (ISCA)
inferredcites →https://doi.org/10.1109/iscas45731.2020.9181266openalex-snapshot
Modified Compressed Sparse Row Format for Accelerated FPGA-Based Sparse Matrix Multiplication
inferredcites →https://doi.org/10.1109/iscas46773.2023.10181734openalex-snapshot
eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication
inferredcites →https://doi.org/10.1109/jstsp.2010.2103924openalex-snapshot
Sparse Matrix Transform for Hyperspectral Image Processing
inferredcites →https://doi.org/10.1109/micro50266.2020.00068openalex-snapshot
MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product
inferredcites →https://doi.org/10.1109/scala.2018.00011openalex-snapshot
Low Thread-Count Gustavson: A Multithreaded Algorithm for Sparse Matrix-Matrix Multiplication Using Perfect Hashing
inferredcites →https://doi.org/10.1109/tcad.2019.2912923openalex-snapshot
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis
inferredcites →https://doi.org/10.1109/tcad.2023.3281714openalex-snapshot
Algorithm/Hardware Co-Optimization for Sparsity-Aware SpMM Acceleration of GNNs
inferredcites →https://doi.org/10.1109/tcad.2023.3281715openalex-snapshot
Efficient FPGA-Based Sparse Matrix–Vector Multiplication With Data Reuse-Aware Compression
inferredcites →https://doi.org/10.1109/tcad.2023.3281719openalex-snapshot
An Efficient Gustavson-Based Sparse Matrix–Matrix Multiplication Accelerator on Embedded FPGAs
inferredcites →https://doi.org/10.1109/tcsii.2023.3344681openalex-snapshot
Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial
inferredcites →https://doi.org/10.1109/tsipn.2017.2731051openalex-snapshot
Network Topology Inference from Spectral Templates
inferredcites →https://doi.org/10.1109/tvlsi.2024.3355499openalex-snapshot
FSpGEMM: A Framework for Accelerating Sparse General Matrix–Matrix Multiplication Using Gustavson’s Algorithm on FPGAs
inferredcites →https://doi.org/10.1137/1.9781611970739openalex-snapshot
Numerical Methods for Large Eigenvalue Problems
inferredcites →https://doi.org/10.1145/2049662.2049663openalex-snapshot
The university of Florida sparse matrix collection
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3182172openalex-snapshot
Dynamic Energy Management of FPGA Accelerators in Embedded Systems
inferredcites →https://doi.org/10.1145/3289185openalex-snapshot
[DL] A Survey of FPGA-based Neural Network Inference Accelerators
inferredcites →https://doi.org/10.1145/3350755.3400216openalex-snapshot
Bandwidth Optimized Parallel Algorithms for Sparse Matrix-Matrix Multiplication using Propagation Blocking
inferredcites →https://doi.org/10.1145/3355399openalex-snapshot
Resource Management and Scheduling in Distributed Stream Processing Systems
inferredcites →https://doi.org/10.1145/3385412.3385963openalex-snapshot
Automatic generation of efficient sparse tensor format conversion routines
inferredcites →https://doi.org/10.1145/3445814.3446702openalex-snapshot
Gamma: leveraging Gustavson’s algorithm to accelerate sparse matrix multiplication
inferredcites →https://doi.org/10.1145/3458744openalex-snapshot
50th International Conference on Parallel Processing Workshop
inferredcites →https://doi.org/10.1145/3458744.3473352openalex-snapshot
Support Convolution of CNN with Compression Sparse Matrix Multiplication Flow in TVM
inferredcites →https://doi.org/10.1145/3490422.3502357openalex-snapshot
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inferredcites →https://doi.org/10.1145/3490422.3502368openalex-snapshot
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
inferredcites →https://doi.org/10.1145/3550075openalex-snapshot
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator
inferredcites →https://doi.org/10.1145/355791.355796openalex-snapshot
Two Fast Algorithms for Sparse Matrices: Multiplication and Permuted Transposition
inferredcites →https://doi.org/10.1145/3566097.3567839openalex-snapshot
Towards High-Bandwidth-Utilization SpMV on FPGAs via Partial Vector Duplication
inferredcites →https://doi.org/10.1145/3626202.3637562openalex-snapshot
FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs
inferredcites →https://doi.org/10.1145/567806.567810openalex-snapshot
An overview of the sparse basic linear algebra subprograms
inferredcites →https://doi.org/10.1177/1094342011403516openalex-snapshot
The Combinatorial BLAS: design, implementation, and applications
inferredcites →https://doi.org/10.1287/opre.9.6.841openalex-snapshot
Parallel Sequencing and Assembly Line Problems
inferredcites →https://doi.org/10.1609/aaai.v37i7.26055openalex-snapshot
On the Expressive Flexibility of Self-Attention Matrices
inferredcites →https://doi.org/10.2172/1435688openalex-snapshot
Sparse Matrix-Matrix Multiplication on Multilevel Memory Architectures: Algorithms and Experiments
inferredcites →https://doi.org/10.2312/sca/sca10/065-073openalex-snapshot
A Parallel Multigrid Poisson Solver for Fluids Simulation on Large Grids
inferredcites →https://doi.org/10.23919/date56975.2023.10136958openalex-snapshot
Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches
inferredcites →https://doi.org/10.48550/arxiv.1909.01315openalex-snapshot
Deep Graph Library: A Graph-Centric, Highly-Performant Package for Graph Neural Networks
inferredcites →https://doi.org/10.48550/arxiv.2104.12369openalex-snapshot
PanGu-$α$: Large-scale Autoregressive Pretrained Chinese Language Models with Auto-parallel Computation
inferredcites →https://doi.org/10.48550/arxiv.2308.00106openalex-snapshot
Entropy Maximization in Sparse Matrix by Vector Multiplication ($\max_E SpMV$)
inferredcites →https://doi.org/10.7873/date.2013openalex-snapshot
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.neunet.2025.107256openalex-snapshot
Spiking neural networks on FPGA: A survey of methodologies and recent advancements
inferred← citeshttps://doi.org/10.1016/j.vlsi.2025.102629openalex-snapshot
Hessian-driven N:M sparsity and quantization co-optimization for edge device deployment
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408479openalex-snapshot
Swift: High-Performance Sparse-Dense Matrix Multiplication on GPUs
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3703795openalex-snapshot
SpMM-GO: Sparse Matrix-Matrix Multiplication Acceleration via Hybrid Gustavson and Outer-Product Dataflows
inferred← citeshttps://doi.org/10.1145/3797905.3807876openalex-snapshot
CipherSkip: Efficient Sparse Matrix Multiplication with FHE
inferred← citeshttps://doi.org/10.1145/3829368openalex-snapshot
A Perspective on the Topics from a Selection of Papers from the First 20 Years of the International Symposium on Applied Reconfigurable Computing (ARC)
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AiSpGEMM: Accelerating Imbalanced SpGEMM on FPGAs with Flexible Interconnect and Intra-row Parallel Merging
inferred← citeshttps://doi.org/10.3390/act14020050openalex-snapshot
A Light-Weight Grasping Pose Estimation Method for Mobile Robotic Arms Based on Depthwise Separable Convolution
inferred← citeshttps://doi.org/10.3390/electronics14234664openalex-snapshot
An Efficient Detection Method for Wafer-Test-Induced Defects
inferred← citeshttps://doi.org/10.3390/info16100914openalex-snapshot
Convolutional Neural Network Acceleration Techniques Based on FPGA Platforms: Principles, Methods, and Challenges
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Domain-Specific Acceleration of Gravity Forward Modeling via Hardware–Software Co-Design
inferred← citeshttps://doi.org/10.5753/sscad_estendido.2025.15856openalex-snapshot
Análise e Comparação de Estratégias de Implementação Física de Multiplicadores Matriciais
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