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Partitioned first-level cache design for clustered microarchitectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/40.621212openalex-snapshot
Two fast and high-associativity cache schemes
inferredcites →https://doi.org/10.1109/hpca.2000.824360openalex-snapshot
A technique for high bandwidth and deterministic low latency load/store accesses to multiple cache banks
inferredcites →https://doi.org/10.1145/223982.224439openalex-snapshot
Next cache line and set prediction
inferredcites →https://doi.org/10.1145/264107.264201openalex-snapshot
Complexity-effective superscalar processors
inferredcites →https://doi.org/10.1145/300979.300983openalex-snapshot
Speculation techniques for improving load related instruction scheduling
inferredcites →https://doi.org/10.1145/48012.48037openalex-snapshot
Cache performance of operating system and multiprogramming workloads
inferredcites →https://doi.org/10.1145/74925.74941openalex-snapshot
Inexpensive implementations of set-associativity
inferredcites →https://doi.org/10.5555/255235.255250openalex-snapshot
Two-ported cache alternatives for superscalar processors
inferredcites →https://doi.org/10.5555/320080.320101openalex-snapshot
Access region locality for high-bandwidth processor memory system design
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11549468_58openalex-snapshot
Dynamic Partition of Memory Reference Instructions – A Register Guided Approach
inferred← citeshttps://doi.org/10.1007/978-1-4419-0263-4_3openalex-snapshot
Composable Multicore Chips
inferred← citeshttps://doi.org/10.1007/978-3-540-27866-5_68openalex-snapshot
Contents Management in First-Level Multibanked Data Caches
inferred← citeshttps://doi.org/10.1007/978-3-642-17752-1_12openalex-snapshot
L1 Data Cache Power Reduction Using a Forwarding Predictor
inferred← citeshttps://doi.org/10.1016/j.jksuci.2015.06.003openalex-snapshot
A high level implementation and performance evaluation of level-I asynchronous cache on FPGA
inferred← citeshttps://doi.org/10.1016/j.sysarc.2009.09.002openalex-snapshot
Access region cache with register guided memory reference partitioning
inferred← citeshttps://doi.org/10.1016/j.sysarc.2010.10.002openalex-snapshot
Stack filter: Reducing L1 data cache power consumption
inferred← citeshttps://doi.org/10.1109/ccece.2007.242openalex-snapshot
A Thread Specific Load Balancing Technique for a Clustered SMT Architecture
inferred← citeshttps://doi.org/10.1109/dft.2012.6378206openalex-snapshot
Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors
inferred← citeshttps://doi.org/10.1109/hpca.2005.21openalex-snapshot
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
inferred← citeshttps://doi.org/10.1109/interact.2005.8openalex-snapshot
Hybrid Compiler and Microarchitecture Technique for Cache Traffic Optimization
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536226openalex-snapshot
Efficient resources assignment schemes for clustered multithreaded processors
inferred← citeshttps://doi.org/10.1109/isca.2005.47openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferred← citeshttps://doi.org/10.1109/ispass.2005.1430566openalex-snapshot
Partitioning Multi-Threaded Processors with a Large Number of Threads
inferred← citeshttps://doi.org/10.1109/ispass.2006.1620794openalex-snapshot
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity
inferred← citeshttps://doi.org/10.1109/lpe.2005.195484openalex-snapshot
Understanding the energy efficiency of SMT and CMP with multiclustering
inferred← citeshttps://doi.org/10.1109/micro.2007.41openalex-snapshot
Composable Lightweight Processors
inferred← citeshttps://doi.org/10.1109/rtcsa.2015.29openalex-snapshot
Memory Pressure Balancing on Virtualized Servers
inferred← citeshttps://doi.org/10.1109/sbac-pad.2008.30openalex-snapshot
Hiding Communication Delays in Clustered Microarchitectures
inferred← citeshttps://doi.org/10.1109/tc.2005.163openalex-snapshot
Distributed Data Cache Designs for Clustered VLIW Processors
inferred← citeshttps://doi.org/10.1109/tc.2009.57openalex-snapshot
Store Buffer Design for Multibanked Data Caches
inferred← citeshttps://doi.org/10.1142/s0218126612500570openalex-snapshot
REDUCING CACHE HIERARCHY ENERGY CONSUMPTION BY PREDICTING FORWARDING AND DISABLING ASSOCIATIVE SETS
inferred← citeshttps://doi.org/10.1145/1006209.1006254openalex-snapshot
Back-end assignment schemes for clustered multithreaded processors
inferred← citeshttps://doi.org/10.1145/1054943.1054950openalex-snapshot
Cache organizations for clustered microarchitectures
inferred← citeshttps://doi.org/10.1145/1077603.1077616openalex-snapshot
Understanding the energy efficiency of SMT and CMP with multiclustering
inferred← citeshttps://doi.org/10.1145/1080695.1070009openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferred← citeshttps://doi.org/10.1145/1629435.1629472openalex-snapshot
Stack oriented data cache filtering
inferred← citeshttps://doi.org/10.1177/10943420251347461openalex-snapshot
Technology trends in computing hardware and their impacts on high-performance scientific computing Part II: Memory systems, interconnects, and system integration
inferred← citeshttps://doi.org/10.5555/1331699.1331707openalex-snapshot
Optimal versus Heuristic Global Code Scheduling
inferred← citeshttps://doi.org/10.5555/1331699.1331733openalex-snapshot
Composable Lightweight Processors
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