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PowerHerd

https://doi.org/10.1145/782814.782830
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/0470841915.ch2openalex-snapshot
Interconnection Networks
inferredcites →https://doi.org/10.1109/40.782564openalex-snapshot
Design challenges of technology scaling
inferredcites →https://doi.org/10.1109/40.988687openalex-snapshot
The Alpha 21364 network architecture
inferredcites →https://doi.org/10.1109/hpca.2001.903261openalex-snapshot
Dynamic thermal management for high-performance microprocessors
inferredcites →https://doi.org/10.1109/hpca.2002.995694openalex-snapshot
Microarchitectural simulation and control of di/dt-induced power supply voltage variation
inferredcites →https://doi.org/10.1109/hpca.2002.995695openalex-snapshot
Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management
inferredcites →https://doi.org/10.1109/hpca.2003.1183526openalex-snapshot
Control techniques to eliminate voltage emergencies in high performance processors
inferredcites →https://doi.org/10.1109/hpca.2003.1183527openalex-snapshot
Dynamic voltage scaling with links for power optimization of interconnection networks
inferredcites →https://doi.org/10.1109/iccd.1997.628902openalex-snapshot
Power constrained design of multiprocessor interconnection networks
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1115/1.801683openalex-snapshot
Thermal management of microelectronic equipment : heat transfer theory, analysis methods, and design practices
inferredcites →https://doi.org/10.1145/378239.379048openalex-snapshot
Route packets, net wires
inferredcites →https://doi.org/10.1145/513918.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.1145/581199.581221openalex-snapshot
An adaptive low-power transmission scheme for on-chip networks
inferredcites →https://doi.org/10.1145/871506.871531openalex-snapshot
Leakage power modeling and optimization in interconnection networks
inferredcites →https://doi.org/10.2307/2288958openalex-snapshot
Classical and Modern Regression With Applications.
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-642-11802-9_13openalex-snapshot
Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
inferred← citeshttps://doi.org/10.1007/s10617-013-9114-5openalex-snapshot
High-level customization framework for application-specific NoC architectures
inferred← citeshttps://doi.org/10.1007/s42514-019-00009-5openalex-snapshot
Low-power and high-performance adaptive routing in on-chip networks
inferred← citeshttps://doi.org/10.1016/j.jpdc.2010.06.001openalex-snapshot
Integration of admission, congestion, and peak power control in QoS-aware clusters
inferred← citeshttps://doi.org/10.1016/j.jpdc.2010.09.005openalex-snapshot
RAFT: A router architecture with frequency tuning for on-chip networks
inferred← citeshttps://doi.org/10.1080/00207217.2015.1017841openalex-snapshot
Performance evaluation of a routing algorithm based on Hopfield Neural Network for network-on-chip
inferred← citeshttps://doi.org/10.1109/dsd.2010.24openalex-snapshot
Power Distribution in NoCs Through a Fuzzy Based Selection Strategy for Adaptive Routing
inferred← citeshttps://doi.org/10.1109/icasic.2007.4415875openalex-snapshot
A power-aware adaptive routing scheme for network on a chip
inferred← citeshttps://doi.org/10.1109/icdsp.2009.5201090openalex-snapshot
Node resource management for DSP applications on 3D Network-on-Chip architecture
inferred← citeshttps://doi.org/10.1109/icecs.2008.4674879openalex-snapshot
PAMPR: Power-aware and minimum path routing algorithm for NoCs
inferred← citeshttps://doi.org/10.1109/icnp.2004.1348125openalex-snapshot
A feasibility study for power management in LAN switches
inferred← citeshttps://doi.org/10.1109/icpp.2005.59openalex-snapshot
Peak Power Control for a QoS Capable On-Chip Network
inferred← citeshttps://doi.org/10.1109/mcsoc.2012.20openalex-snapshot
Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems
inferred← citeshttps://doi.org/10.1109/micro.2004.35openalex-snapshot
Thermal Modeling, Characterization and Management of On-Chip Networks
inferred← citeshttps://doi.org/10.1109/tc.2007.70789openalex-snapshot
A Dynamic Slack Management Technique for Real-Time Distributed Embedded Systems
inferred← citeshttps://doi.org/10.1109/tcad.2005.852438openalex-snapshot
PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2011229openalex-snapshot
Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip
inferred← citeshttps://doi.org/10.1145/1084834.1084856openalex-snapshot
Key research problems in NoC design
inferred← citeshttps://doi.org/10.1145/1176760.1176807openalex-snapshot
High-level power analysis for multi-core chips
inferred← citeshttps://doi.org/10.1145/1391469.1391627openalex-snapshot
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
inferred← citeshttps://doi.org/10.1145/1394608.1382141openalex-snapshot
Virtual Circuit Tree Multicasting
inferred← citeshttps://doi.org/10.1145/1669112.1669151openalex-snapshot
A case for dynamic frequency tuning in on-chip networks
inferred← citeshttps://doi.org/10.1145/2435227.2435252openalex-snapshot
Moths
inferred← citeshttps://doi.org/10.1587/elex.8.1102openalex-snapshot
Minimal fully adaptive fuzzy-based routing algorithm for Networks-on-Chip
inferred← citeshttps://doi.org/10.5445/ir/1000012895openalex-snapshot
Runtime Adaptive System-on-Chip Communication Architecture
inferred← citeshttps://doi.org/10.5555/2492708.2492829openalex-snapshot
Dynamic directories: a mechanism for reducing on-chip interconnect power in multicores
inferred← citeshttps://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
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