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Thermal Modeling, Characterization and Management of On-Chip Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/55.974803openalex-snapshot
Analytical thermal model for multilevel VLSI interconnects incorporating via effect
inferredcites →https://doi.org/10.1109/hpca.2001.903261openalex-snapshot
Dynamic thermal management for high-performance microprocessors
inferredcites →https://doi.org/10.1109/hpca.2003.1183527openalex-snapshot
Dynamic voltage scaling with links for power optimization of interconnection networks
inferredcites →https://doi.org/10.1109/iccd.1997.628902openalex-snapshot
Power constrained design of multiprocessor interconnection networks
inferredcites →https://doi.org/10.1109/isca.2003.1206984openalex-snapshot
Temperature-aware microarchitecture
inferredcites →https://doi.org/10.1109/isscc.2004.1332591openalex-snapshot
Design and implementation of the POWER5/spl trade/ microprocessor
inferredcites →https://doi.org/10.1109/l-ca.2002.7openalex-snapshot
Migration in Single Chip Multiprocessors
inferredcites →https://doi.org/10.1109/lpe.2003.1231942openalex-snapshot
Energy characterization of a tiled architecture processor with on-chip networks
inferredcites →https://doi.org/10.1109/micro.2002.1176258openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.1109/micro.2003.1253187openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.1115/1.801683openalex-snapshot
Thermal management of microelectronic equipment : heat transfer theory, analysis methods, and design practices
inferredcites →https://doi.org/10.1145/1028176.1006733openalex-snapshot
Evaluation of the Raw Microprocessor
inferredcites →https://doi.org/10.1145/378239.379045openalex-snapshot
Addressing the system-on-a-chip interconnect woes through communication-based design
inferredcites →https://doi.org/10.1145/782814.782831openalex-snapshot
Predictive dynamic thermal management for multimedia applications
inferredcites →https://doi.org/10.1145/859618.859620openalex-snapshot
Temperature-aware microarchitecture
inferredcites →https://doi.org/10.1145/859618.859667openalex-snapshot
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
inferredcites →https://doi.org/10.1145/871506.871610openalex-snapshot
Energy characterization of a tiled architecture processor with on-chip networks
inferredcites →https://doi.org/10.1145/871506.871620openalex-snapshot
Energy optimization techniques in cluster interconnects
inferredcites →https://doi.org/10.1145/996566.996749openalex-snapshot
Design and implementation of the POWER5™ microprocessor
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Opinion Mining and Sentiment Analysis
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ArR-DTM: A routing-based DTM for 3D NoCs by adaptive degree regulation
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Collaborative thermal- and traffic-aware adaptive routing scheme for 3D network-on-chip systems
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High Performance Virtual Channel Based Fully Adaptive 3D NoC Routing for Congestion and Thermal Problem
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A Thermal driven genetic algorithm for three dimensional Network-on-Chip systems
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FMoTAR: A Fast Multi-objective Thermal Aware Routing Algorithm for Three-Dimensional Network-on-Chips
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Chapter 2: Literature Survey
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Practical Dynamic Thermal Management on Intel Desktop Computer
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System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design
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A Survey of MPSoC Management toward Self-Awareness
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Self-Adaptive SoCs for Dependability
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Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip
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Performance Analysis of Temperature Management Approaches in Networks-on-Chip
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Analysis of Characteristic the Heat Transfer on Mine-Used Inverter
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Cost Effective Routing Implementations for On-chip Networks
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Thermal Uniformity-Aware Application Mapping for Network-on-Chip Design
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A Review of the Design Challenges for the 3-D on Chip Network Paradigms
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Dynamic directories: a mechanism for reducing on-chip interconnect power in multicores
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TAPP: temperature-aware application mapping for NoC-based many-core processors
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