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Network-on-Chip

https://doi.org/10.1201/b17748
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inferred← citeshttps://doi.org/10.1007/978-3-031-97709-1_23openalex-snapshot
Implementation of Wormhole Switching with Virtual Channels to Mitigate Deadlock
inferred← citeshttps://doi.org/10.1007/s44291-024-00027-wopenalex-snapshot
A comprehensive study and holistic review of empowering network-on-chip application mapping through machine learning techniques
inferred← citeshttps://doi.org/10.1109/access.2023.3329233openalex-snapshot
A Survey on Dynamic Application Mapping Approaches for Real-Time Network-on-Chip-Based Platforms
inferred← citeshttps://doi.org/10.1109/aic66080.2025.11212129openalex-snapshot
Hash Based Smart Shortcut Links Applied Optimized Energy Efficient Topology Augmentation in 3-D Mesh
inferred← citeshttps://doi.org/10.1109/dft66274.2025.11257459openalex-snapshot
Reliability and Performance Evaluation of a Fault-Tolerant MPSoC Interconnection Architecture
inferred← citeshttps://doi.org/10.1109/dspa69176.2026.11476731openalex-snapshot
A Scalable Inter-Module Communication Approach for High-Complexity DSP Systems
inferred← citeshttps://doi.org/10.1109/ises67504.2025.00063openalex-snapshot
Adaptive Task Mapping in NoC Systems Using Salp Swarm and Markov Decision Processes
inferred← citeshttps://doi.org/10.1109/isqed60706.2024.10528773openalex-snapshot
Thermo-Attack Resiliency: Addressing a New Vulnerability in Opto-Electrical Network-on-Chips
inferred← citeshttps://doi.org/10.1109/isqed65160.2025.11014406openalex-snapshot
Reinforcement Learning for Testtime Optimization in the Network-on-Chip based Systems
inferred← citeshttps://doi.org/10.1109/lascas64004.2025.10966348openalex-snapshot
Hardening an AMBA-AXI Network Interface for a Reliable Network-on-Chip
inferred← citeshttps://doi.org/10.1109/lats70329.2026.11480296openalex-snapshot
Resilience Analysis of a Fault-Tolerant MPSoC Interconnection Architecture Under SEU Fault Injection
inferred← citeshttps://doi.org/10.1109/nocarc64615.2024.10749907openalex-snapshot
NoCSNet: Network-on-Chip Security Assessment Under Thermal Attacks Using Deep Neural Network
inferred← citeshttps://doi.org/10.1109/sds57574.2022.10062950openalex-snapshot
Optimizing System-on-Chip Performance Using AI and SDN: Approaches and Challenges
inferred← citeshttps://doi.org/10.1109/tcad.2021.3101406openalex-snapshot
BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3690001openalex-snapshot
Topology Optimization of 3-D NoC for High-Speed Data Acquisition Systems via Deep Reinforcement Learning
inferred← citeshttps://doi.org/10.1109/vdat63601.2024.10705744openalex-snapshot
Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA
inferred← citeshttps://doi.org/10.1117/12.3015622openalex-snapshot
High performance and low area interconnect structure based on AXI
inferred← citeshttps://doi.org/10.1142/s0218126618502262openalex-snapshot
A Communication Probability-Based Mapping Algorithm for Mesh-Based Network-on-Chip Systems
inferred← citeshttps://doi.org/10.1142/s0218126625502160openalex-snapshot
Dynamic Analysis of Network on Chip Topologies and Designing a Novel Mesh of Spidergon Topology
inferred← citeshttps://doi.org/10.1145/3055512openalex-snapshot
Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform
inferred← citeshttps://doi.org/10.1145/3291532openalex-snapshot
Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip
inferred← citeshttps://doi.org/10.1145/3565478.3572327openalex-snapshot
Data and Fault Aware Routing Algorithm for NoC Based Approximate Computing
inferred← citeshttps://doi.org/10.12720/jcm.13.4.193-197openalex-snapshot
3D Network-on-Chip Based Median Filter Implementation
inferred← citeshttps://doi.org/10.14210/cotb.v15.p172-178openalex-snapshot
Interface de rede AMBA-AXI para uma rede-em-chip confiável
inferred← citeshttps://doi.org/10.1587/transfun.e101.a.2018openalex-snapshot
Bounds on the Asymptotic Rate for Capacitive Crosstalk Avoidance Codes for On-Chip Buses
inferred← citeshttps://doi.org/10.1587/transfun.e99.a.2155openalex-snapshot
Performance Analysis Based on Density Evolution on Fault Erasure Belief Propagation Decoder
inferred← citeshttps://doi.org/10.4018/ijismd.2017040104openalex-snapshot
An Efficient and Congestion Aware Fuzzy Based Output Selection Strategy for On-Chip Routers
inferred← citeshttps://doi.org/10.5772/intechopen.97341openalex-snapshot
Design and Optimization of Networks-on-Chip
inferred← citeshttps://doi.org/10.70675/ba79c1e5z5886z4391z9ed6zff3c784a335fopenalex-snapshot
Design of a digital baseband transceiver for wireless network-on-chip architectures
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