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Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Task Scheduling for Parallel Systems
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Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach
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Communication and migration energy aware task mapping for reliable multiprocessor systems
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From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations
inferredcites →https://doi.org/10.1016/j.sysarc.2015.06.001openalex-snapshot
Dynamic task mapping for Network-on-Chip based systems
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A fault‐tolerant core mapping technique in networks‐on‐chip
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Tolerance to multiple transient faults for aperiodic tasks in hard real-time systems
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Networks on chips: a new SoC paradigm
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On the design and analysis of fault tolerant NoC architecture using spare routers
inferredcites →https://doi.org/10.1109/date.2008.4484787openalex-snapshot
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology
inferredcites →https://doi.org/10.1109/date.2008.4484825openalex-snapshot
Synthesis of Fault-Tolerant Embedded Systems
inferredcites →https://doi.org/10.1109/date.2009.5090627openalex-snapshot
A highly resilient routing algorithm for fault-tolerant NoCs
inferredcites →https://doi.org/10.1109/date.2009.5090700openalex-snapshot
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
inferredcites →https://doi.org/10.1109/date.2011.5763113openalex-snapshot
FARM: Fault-aware resource management in NoC-based multiprocessor platforms
inferredcites →https://doi.org/10.1109/dsn.2002.1028901openalex-snapshot
Impact of deep submicron technology on dependability of VLSI circuits
inferredcites →https://doi.org/10.1109/ecrts.2014.15openalex-snapshot
Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks
inferredcites →https://doi.org/10.1109/hpcc.and.euc.2013.125openalex-snapshot
An Efficient Topology Reconfiguration Algorithm for NoC Based Multiprocessor Arrays
inferredcites →https://doi.org/10.1109/iccd.2012.6378613openalex-snapshot
Exploiting microarchitectural redundancy for defect tolerance
inferredcites →https://doi.org/10.1109/isca.2005.44openalex-snapshot
Rescue: A Microarchitecture for Testability and Defect Tolerance
inferredcites →https://doi.org/10.1109/issoc.2008.4694878openalex-snapshot
Congestion-aware task mapping in heterogeneous MPSoCs
inferredcites →https://doi.org/10.1109/isvdat.2014.6881036openalex-snapshot
A spare link based reliable Network-on-Chip design
inferredcites →https://doi.org/10.1109/mm.2003.1225959openalex-snapshot
Trends and challenges in VLSI circuit reliability
inferredcites →https://doi.org/10.1109/mwscas.2011.6026672openalex-snapshot
Reliability improvement in multicore architectures through computing in embedded memory
inferredcites →https://doi.org/10.1109/prfts.1997.640132openalex-snapshot
Fault-tolerant real-time scheduling using passive replicas
inferredcites →https://doi.org/10.1109/recosoc.2013.6581540openalex-snapshot
Energy-aware dynamic reconfiguration of communication-centric applications for reliable MPSoCs
inferredcites →https://doi.org/10.1109/rsp.2012.6380704openalex-snapshot
Fault-aware task re-mapping for throughput constrained multimedia applications on NoC-based MPSoCs
inferredcites →https://doi.org/10.1109/scd.2011.6068747openalex-snapshot
Resilient dynamic task scheduling for unreliable heterogeneous MPSoCs
inferredcites →https://doi.org/10.1109/tc.2011.32openalex-snapshot
Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip
inferredcites →https://doi.org/10.1109/tcad.2010.2048399openalex-snapshot
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
inferredcites →https://doi.org/10.1109/test.2008.4700562openalex-snapshot
A Cost Analysis Framework for Multi-core Systems with Spares
inferredcites →https://doi.org/10.1109/tvlsi.2008.2002108openalex-snapshot
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems
inferredcites →https://doi.org/10.1145/1289816.1289824openalex-snapshot
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules
inferredcites →https://doi.org/10.1145/1403375.1403591openalex-snapshot
Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology
inferredcites →https://doi.org/10.1145/1403375.1403644openalex-snapshot
Synthesis of fault-tolerant embedded systems
inferredcites →https://doi.org/10.1145/1878961.1879014openalex-snapshot
A task remapping technique for reliable multi-core embedded systems
inferredcites →https://doi.org/10.1145/2039370.2039409openalex-snapshot
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
inferredcites →https://doi.org/10.1145/2665071openalex-snapshot
Execution Trace--Driven Energy-Reliability Optimization for Multimedia MPSoCs
inferredcites →https://doi.org/10.1145/2700417openalex-snapshot
Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm
inferredcites →https://doi.org/10.1145/2892633openalex-snapshot
Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip
inferredcites →https://doi.org/10.1145/996566.996588openalex-snapshot
Design and reliability challenges in nanometer technologies
inferredcites →https://doi.org/10.1147/rd.516.0733openalex-snapshot
System power management support in the IBM POWER6 microprocessor
inferredcites →https://doi.org/10.1201/9781315216072openalex-snapshot
Network-on-Chip: The Next Generation of System-on-Chip Integration
inferredcites →https://doi.org/10.5555/1874620.1874628openalex-snapshot
A highly resilient routing algorithm for fault-tolerant NoCs
inferredcites →https://doi.org/10.5555/1950815.1950906openalex-snapshot
On the design and analysis of fault tolerant NoC architecture using spare routers
inferredcites →https://doi.org/10.7873/date.2013.149openalex-snapshot
Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Sixer: A low-overhead, fully-distributed test scheme with guaranteed delivery of packets in networks-on-chip
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Task mapping and scheduling for network-on-chip based multi-core platform with transient faults
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A survey on fault-tolerant application mapping techniques for Network-on-Chip
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A permanent fault tolerant dynamic task allocation approach for Network-on-Chip based multicore systems
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Dynamic Task Mapping and Scheduling with Temperature-Awareness on Network-on-Chip based Multicore Systems
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Dynamic task allocation and scheduling with contention-awareness for Network-on-Chip based multicore systems
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Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip
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Reliability-aware application mapping onto mesh based Network-on-Chip
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Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC
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A Novel and Adaptive Transient Fault-Tolerant Algorithm Considering Timing Constraint on Heterogeneous Systems
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Software-Level TMR Approach for On-Board Data Processing in Space Applications
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ConBin: a Performance-Convergence Framework for Wafer-Scale Chip Binning
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Heaping of Sorrow Upon Sorrow
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A Dynamic Resource Allocation Strategy for NoC Based Multicore Systems with Permanent Faults
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LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems
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An Adaptive Software Defined Network-on-Chip (SD-NoC) For Varying Network Resources in Offering Optimal Service Quality: Survey
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Enhancing Reliability and Energy Efficiency in Many-Core Processors Through Fault-Tolerant Network-on-Chip
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CMV: Clustered Majority Voting Reliability-Aware Task Scheduling for Multicore Real-Time Systems
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Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks
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A Reconfiguration-Based Fault-Tolerant Anti-Lock Brake-by-Wire System
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Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip
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An Enhanced Dynamic Weighted Incremental Technique for QoS Support in NoC
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Adaptive Task Allocation and Scheduling on NoC-based Multicore Platforms with Multitasking Processors
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Fault-Tolerant Topology Reconfiguration Framework for NoC-Based Multiprocessor Arrays via Bipartite Matching and Reinforcement Learning
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Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey
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A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing
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Energy Efficient, Real-time and Reliable Task Deployment on NoC-based Multicores with DVFS
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A new architecture for online error detection and isolation in network on chip
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