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CMOS Time-Mode Circuits and Systems
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inferred← citeshttps://doi.org/10.1007/978-3-030-40971-5_27openalex-snapshot
Theoretical Estimates of the Accuracy of Determination of Geometric Parameters of Objects on Digital Images
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180-nm 20 ps Resolution 0.29 LSB Single-Shot Precision Vernier Delay Line Based Time-to-Digital Converter
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Multipath Delay Cell-Based Coupled Oscillators for $${\varSigma }{\varDelta }$$ Time-to-Digital Converters
inferred← citeshttps://doi.org/10.1007/s00034-019-01233-8openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10470-019-01544-5openalex-snapshot
CMOS time-mode smart temperature sensor using programmable temperature compensation devices and $$\Delta \Sigma$$ time-to-digital converter
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A scalable high-linearity two-step DTC-assisted voltage–to-time converter with rail-to-rail input-range for time-based circuits
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Time-to-digital conversion techniques: a survey of recent developments
inferred← citeshttps://doi.org/10.1016/j.measurement.2024.115313openalex-snapshot
Novel machine learning-driven optimizing decoding solutions for FPGA-based time-to-digital converters
inferred← citeshttps://doi.org/10.1016/j.mejo.2018.05.010openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.mejo.2019.104695openalex-snapshot
Highly-linear wide-range voltage-controlled delay element with body bias technique
inferred← citeshttps://doi.org/10.1049/el.2018.6288openalex-snapshot
High‐precision differential time integrator based on time adder
inferred← citeshttps://doi.org/10.1049/iet-cds.2017.0327openalex-snapshot
Design techniques of all‐digital arithmetic units for time‐mode signal processing
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Digital instrument with configurable hardware and firmware for multi-channel time measures
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Digital Instrument for Time Measurements: Small, Portable, High–Performance, Fully Programmable
inferred← citeshttps://doi.org/10.1109/access.2021.3113033openalex-snapshot
Cross-Talk Issues in Time Measurements
inferred← citeshttps://doi.org/10.1109/ebccsp.2016.7605284openalex-snapshot
Optimized design of successive approximation time-to-digital converter with single set of delay lines
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Frequency-domain adaptive-resolution level-crossing-sampling ADC
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Behavioral Modelling and Optimization of a Cyclic Feedback-Based Successive Approximation TDC with Dynamic Delay Equalization
inferred← citeshttps://doi.org/10.1109/ebccsp51266.2020.9291366openalex-snapshot
Successive Approximation Time-to-Digital Converters
inferred← citeshttps://doi.org/10.1109/icam.2017.8242183openalex-snapshot
Design techniques of all-digital time integrators for time-mode signal processing
inferred← citeshttps://doi.org/10.1109/icee.2018.8472578openalex-snapshot
Low-power Time-to-Digital Converter Based on Vernier Gated-Ring-Oscillator
inferred← citeshttps://doi.org/10.1109/lssc.2021.3069796openalex-snapshot
Differential Edge-Modulated Signaling With Encoded Clock and Dynamic Data Rate Scaling
inferred← citeshttps://doi.org/10.1109/mwscas.2017.8053014openalex-snapshot
Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integrator
inferred← citeshttps://doi.org/10.1109/mwscas.2017.8053096openalex-snapshot
1-1 MASH ΔΣ time-to-digital converter with differential cascode time integrator
inferred← citeshttps://doi.org/10.1109/mwscas.2019.8885185openalex-snapshot
All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time Integrator
inferred← citeshttps://doi.org/10.1109/mwscas.2019.8885394openalex-snapshot
A 500-MS/s 8.4-ps Double-Edge Successive Approximation TDC in 65 nm CMOS
inferred← citeshttps://doi.org/10.1109/mwscas48704.2020.9184604openalex-snapshot
A Wide Input-Range, Low-Power and Highly Flexible 18 Bit Time-to-Digital Converter with Compact Differential Circuit Topology
inferred← citeshttps://doi.org/10.1109/norchip.2018.8573459openalex-snapshot
High-speed Sampling System in CMOS
inferred← citeshttps://doi.org/10.1109/nss/mic42101.2019.9059963openalex-snapshot
Time-Mode analysis of Crosstalk interference in a FPGA-based TDC implementation
inferred← citeshttps://doi.org/10.1109/nssmic.2018.8824537openalex-snapshot
Hardware Description Language Phase-Locked Loop (HDL-PLL) Open Architecture for FPGAs
inferred← citeshttps://doi.org/10.1109/prime.2018.8430374openalex-snapshot
11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology
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A 96 dB Input Dynamic Range Galvanic Skin Response Readout IC With 3.5 pArms Input-Referred Noise for Mental Stress Monitoring
inferred← citeshttps://doi.org/10.1109/tcsi.2023.3279231openalex-snapshot
Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication
inferred← citeshttps://doi.org/10.1109/tcsii.2024.3401701openalex-snapshot
Efficient Address-Embedded Time-Domain Implementation of Minima Finders for Soft Error-Correction Decoders
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3541539openalex-snapshot
A Time-Domain Frequency Analyzer Based on Goertzel Algorithm
inferred← citeshttps://doi.org/10.1145/3394885.3431643openalex-snapshot
An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept
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All-Digital Noise-Shaping Time-to-Digital Converters for Mixed-Mode Signal Processing
inferred← citeshttps://doi.org/10.3390/electronics11060902openalex-snapshot
A 3rd-Order FIR Filter Implementation Based on Time-Mode Signal Processing
inferred← citeshttps://doi.org/10.3390/s19051109openalex-snapshot
A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements
inferred← citeshttps://doi.org/10.3390/s23249712openalex-snapshot
A New Successive Time Balancing Time-to-Digital Conversion Method
inferred← citeshttps://doi.org/10.3390/s24175512openalex-snapshot
Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review
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Extension of socs mission capabilities by offering near-zero-power performances and enabling continuous functionality for Iot systems
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