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https://doi.org/10.2139/ssrn.4669088

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inferredcites →https://doi.org/10.1007/978-3-030-15729-6openalex-extracted
An Introduction to Machine Learning
inferredcites →https://doi.org/10.1007/s40336-019-00316-5openalex-extracted
The new opportunities for high time resolution clinical TOF PET
inferredcites →https://doi.org/10.1016/j.measurement.2023.112705openalex-extracted
Time-to-digital converters and histogram builders in SPAD arrays for pulsed-LiDAR
inferredcites →https://doi.org/10.1016/j.net.2022.10.010openalex-extracted
Linearity improvement of UltraScale+ FPGA-based time-to-digital converter
inferredcites →https://doi.org/10.1023/a:1008202821328openalex-extracted
Differential Evolution – A Simple and Efficient Heuristic for global Optimization over Continuous Spaces
inferredcites →https://doi.org/10.1049/iet-cds.2020.0026openalex-extracted
Fine resolution delay tuning method to improve the linearity of an unbalanced time‐to‐digital converter on a Xilinx FPGA
inferredcites →https://doi.org/10.1063/1.3563723openalex-extracted
A photoelectron velocity map imaging spectrometer for experiments combining synchrotron and laser radiations
inferredcites →https://doi.org/10.1063/1.3669787openalex-extracted
Time-resolved soft x-ray absorption setup using multi-bunch operation modes at synchrotrons
inferredcites →https://doi.org/10.1063/1.5008610openalex-extracted
An 18-ps TDC using timing adjustment and bin realignment methods in a Cyclone-IV FPGA
inferredcites →https://doi.org/10.1088/0957-0233/26/7/075002openalex-extracted
Quantization error in precision time counters
inferredcites →https://doi.org/10.1093/comjnl/7.2.155openalex-extracted
An efficient method for finding the minimum of a function of several variables without calculating derivatives
inferredcites →https://doi.org/10.1093/comjnl/7.4.308openalex-extracted
A Simplex Method for Function Minimization
inferredcites →https://doi.org/10.1109/19.552156openalex-extracted
Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution
inferredcites →https://doi.org/10.1109/4.16314openalex-extracted
Metastability behavior of CMOS ASIC flip-flops in theory and test
inferredcites →https://doi.org/10.1109/access.2021.3088448openalex-extracted
Time-to-Digital Converter IP-Core for FPGA at State of the Art
inferredcites →https://doi.org/10.1109/access.2021.3109155openalex-extracted
Digital Instrument for Time Measurements: Small, Portable, High–Performance, Fully Programmable
inferredcites →https://doi.org/10.1109/access.2021.3113033openalex-extracted
Cross-Talk Issues in Time Measurements
inferredcites →https://doi.org/10.1109/access.2022.3227462openalex-extracted
Assessment of the Bundle SNSPD Plus FPGA-Based TDC for High-Performance Time Measurements
inferredcites →https://doi.org/10.1109/async.1996.494449openalex-extracted
Characterizing metastability
inferredcites →https://doi.org/10.1109/ebccsp.2019.8836892openalex-extracted
A Novel TDC Scheme: Combinatorial Gray Code Oscillator Based TDC for Low Power and Low Resource Usage Applications
inferredcites →https://doi.org/10.1109/isscs.2015.7203949openalex-extracted
A 23ps resolution Time-to-Digital converter implemented on low-cost FPGA platform
inferredcites →https://doi.org/10.1109/les.2009.2034711openalex-extracted
BOUNCE: A New High-Resolution Time-Interval Measurement Architecture
inferredcites →https://doi.org/10.1109/mixdes.2016.7529741openalex-extracted
Verilog HDL model based thermometer-to-binary encoder with bubble error correction
inferredcites →https://doi.org/10.1109/norchp.2011.6126745openalex-extracted
A digital PLL with a multi-delay coarse-fine TDC
inferredcites →https://doi.org/10.1109/nss/mic42101.2019.9059958openalex-extracted
Very High-Performance 24-Channels Time-to-Digital Converter in Xilinx 20-nm Kintex UltraScale FPGA
inferredcites →https://doi.org/10.1109/nssmic.2008.4775079openalex-extracted
The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay
inferredcites →https://doi.org/10.1109/nssmic.2014.7431149openalex-extracted
Quantization noise in non-homogeneous calibration table of a TCD implemented in FPGA
inferredcites →https://doi.org/10.1109/nssmic.2015.7581245openalex-extracted
8-Channels high-resolution TDC in FPGA
inferredcites →https://doi.org/10.1109/nssmic.2016.8069666openalex-extracted
Fully-migratable TDC architecture for FPGA devices
inferredcites →https://doi.org/10.1109/nssmic.2017.8532676openalex-extracted
A 128-Channel High Performance Time-to-Digital Converter Implemented in an UltraScale FPGA
inferredcites →https://doi.org/10.1109/nssmic.2017.8533060openalex-extracted
Auto-Calibrating TDC for a SoC-FPGA Data Acquisition System
inferredcites →https://doi.org/10.1109/tbcas.2015.2389227openalex-extracted
Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA
inferredcites →https://doi.org/10.1109/tcsi.2014.2340551openalex-extracted
Time-Mode Analog-to-Digital Conversion Using Standard Cells
inferredcites →https://doi.org/10.1109/tcsii.2022.3161650openalex-extracted
A Reconfigurable 5-Channel Ring-Oscillator-Based TDC for Direct Time-of-Flight 3D Imaging
inferredcites →https://doi.org/10.1109/tie.2018.2842787openalex-extracted
Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs
inferredcites →https://doi.org/10.1109/tie.2021.3111563openalex-extracted
Multichannel Time-to-Digital Converters With Automatic Calibration in Xilinx Zynq-7000 FPGA Devices
inferredcites →https://doi.org/10.1109/tie.2023.3322007openalex-extracted
From Multiphase to Novel Single-Phase Multichannel Shift-Clock Fast Counter Time-to-Digital Converter
inferredcites →https://doi.org/10.1109/tim.2016.2534670openalex-extracted
Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs
inferredcites →https://doi.org/10.1109/tim.2018.2886940openalex-extracted
Measurement Uncertainty of Precise Interpolating Time Counters
inferredcites →https://doi.org/10.1109/tim.2019.2932156openalex-extracted
Enhancing Nutt-Based Time-to-Digital Converter Performance With Internal Systematic Averaging
inferredcites →https://doi.org/10.1109/tim.2019.2936717openalex-extracted
A Review of New Time-to-Digital Conversion Techniques
inferredcites →https://doi.org/10.1109/tim.2019.2938436openalex-extracted
Recent Developments and Challenges in FPGA-Based Time-to-Digital Converters
inferredcites →https://doi.org/10.1109/tim.2019.2954173openalex-extracted
An 8-ch LIDAR Receiver Based on TDC With Multi-Interval Detection and Real-Time $In~Situ$ Calibration
inferredcites →https://doi.org/10.1109/tim.2019.2959423openalex-extracted
A High-Linearity Vernier Time-to-Digital Converter on FPGAs With Improved Resolution Using Bidirectional-Operating Vernier Delay Lines
inferredcites →https://doi.org/10.1109/tim.2020.3011490openalex-extracted
Design and Calibration Techniques for a Multichannel FPGA-Based Time-to-Digital Converter in an Object Positioning System
inferredcites →https://doi.org/10.1109/tim.2022.3198442openalex-extracted
High-Resolution Imager Based on Time-to-Space Conversion
inferredcites →https://doi.org/10.1109/tim.2023.3267566openalex-extracted
Trimmed-TDL-Based TDC Architecture for Time-of-Flight Measurements Tested on a Cyclone V FPGA
inferredcites →https://doi.org/10.1109/tim.2023.3271755openalex-extracted
A 1.9 ps-rms Precision Time-to-Amplitude Converter With 782 fs LSB and 0.79%-rms DNL
inferredcites →https://doi.org/10.1109/tns.2011.2141684openalex-extracted
A High-Resolution ( ${< 10}~{\rm ps}$ RMS) 48-Channel Time-to-Digital Converter (TDC) Implemented in a Field Programmable Gate Array (FPGA)
inferredcites →https://doi.org/10.1109/tns.2013.2280909openalex-extracted
The Design of a 16-Channel 15 ps TDC Implemented in a 65 nm FPGA
inferredcites →https://doi.org/10.1109/tns.2015.2475630openalex-extracted
A Nonlinearity Minimization-Oriented Resource-Saving Time-to-Digital Converter Implemented in a 28 nm Xilinx FPGA
inferredcites →https://doi.org/10.1109/tns.2018.2790703openalex-extracted
Design and Characterization of a Low-Cost FPGA-Based TDC
inferredcites →https://doi.org/10.1109/trpms.2018.2874358openalex-extracted
Toward a Full-Flexible and Fast-Prototyping TOF-PET Block Detector Based on TDC-on-FPGA
inferredcites →https://doi.org/10.1109/trpms.2018.2882709openalex-extracted
Auto-Calibrating TDC for an SoC-FPGA Data Acquisition System
inferredcites →https://doi.org/10.1201/b19228openalex-extracted
CMOS Time-Mode Circuits and Systems
inferredcites →https://doi.org/10.3390/electronics11010030openalex-extracted
Bubble-Proof Algorithm for Wave Union TDCs
inferredcites →https://doi.org/10.3390/s21010308openalex-extracted
A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA
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